A 9-b 400 Msample/s pipelined analog-to digital converter in 90nm CMOS

Abstract

A 9-bit 400MS/s pipelined analog-to-digital converter (ADC) targeted for emerging wireless LAN applications is presented. The converter can be clocked up to 500 mega-samples per second (MSPS) with an input bandwidth of 100 MHz, while drawing 93mA from 1.5V. The ADC achieves 8.6 effective number of bits (ENOBs) at 10MHz input and 7.9 ENOBs at 80MHz input, without accounting for calibration or oversampling based enhancements. The architecture is a double-sampled switched-capacitor pipeline that converts on both phases of the sampling clock for improved power efficiency. A skew-insensitive sample-and-hold stage attenuates distortion caused by imperfectly phased sampling clocks.