L. Mensi, L. Colalongo, A. Richelli, Z. Kovács-Vajna
{"title":"A new integrated charge pump architecture using dynamic biasing of pass transistors","authors":"L. Mensi, L. Colalongo, A. Richelli, Z. Kovács-Vajna","doi":"10.1109/ESSCIR.2005.1541564","DOIUrl":null,"url":null,"abstract":"In this paper, a new charge pump architecture is presented: it is based on PMOS pass transistors with dynamic biasing of gates and bodies. By controlling the gate and body voltages of each pass transistor, the voltage loss due to the device threshold is removed and the charge is pumped from one stage to the other with negligible voltage drop. Furthermore, the overdrive voltage of the pass transistors grows progressively from the first to the last boost stage. This new architecture was developed and validated through simulations and experimental measurements on AMS 0.8/spl mu/m standard CMOS technology.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"51 1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"33","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIR.2005.1541564","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 33
Abstract
In this paper, a new charge pump architecture is presented: it is based on PMOS pass transistors with dynamic biasing of gates and bodies. By controlling the gate and body voltages of each pass transistor, the voltage loss due to the device threshold is removed and the charge is pumped from one stage to the other with negligible voltage drop. Furthermore, the overdrive voltage of the pass transistors grows progressively from the first to the last boost stage. This new architecture was developed and validated through simulations and experimental measurements on AMS 0.8/spl mu/m standard CMOS technology.