90nm CMOS的9-b 400 Msample/s流水线模数转换器

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI:10.1109/ESSCIR.2005.1541678

Charles T. Peach, A. Ravi, R. Bishop, K. Soumyanath, D. Allstot

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引用次数: 9

摘要

提出了一种针对新兴无线局域网应用的9位400MS/s流水线模数转换器(ADC)。该转换器可以以每秒500兆采样(MSPS)的频率进行时钟处理，输入带宽为100 MHz，同时从1.5V输出93mA。在不考虑校准或过采样增强的情况下，ADC在10MHz输入时实现8.6有效位数(ENOBs)，在80MHz输入时实现7.9有效位数(ENOBs)。该架构是双采样开关电容管道，可转换采样时钟的两个相位，以提高功率效率。对倾斜不敏感的采样保持级可衰减由不完全相位采样时钟引起的失真。

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A 9-b 400 Msample/s pipelined analog-to digital converter in 90nm CMOS

A 9-bit 400MS/s pipelined analog-to-digital converter (ADC) targeted for emerging wireless LAN applications is presented. The converter can be clocked up to 500 mega-samples per second (MSPS) with an input bandwidth of 100 MHz, while drawing 93mA from 1.5V. The ADC achieves 8.6 effective number of bits (ENOBs) at 10MHz input and 7.9 ENOBs at 80MHz input, without accounting for calibration or oversampling based enhancements. The architecture is a double-sampled switched-capacitor pipeline that converts on both phases of the sampling clock for improved power efficiency. A skew-insensitive sample-and-hold stage attenuates distortion caused by imperfectly phased sampling clocks.

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Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.

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