Low leakage design of LUT-based FPGAs

Abstract

Moving to the 90nm node and below, in FPGA architectures, where there's a large number of inactive transistors, power consumption due to subthreshold current becomes more and more relevant compared with the switching one. In this paper we analyze the leakage current associated to look up tables, the basic elaboration units of LUT-based FPGAs, giving a characterization in terms of timing performance, inactive and active leakage power consumption. We propose a circuit implementation to reduce leakage, avoiding delay and silicon area increase. The adopted solutions are based on multi-threshold and self reverse biasing techniques. As results we reduce the inactive leakage power by 88%, the active one by 64%, having 5% delay degradation and a negligible silicon area increase.