A 3.5Gbit/s post-amplifier in 0.18/spl mu/m CMOS

Abstract

A postamplifier with output buffer implemented in a standard 0.18/spl mu/m 1.8V CMOS technology is proposed. Using broadband techniques for both postamplifier and output buffer, highspeed operation has been achieved. For a differential 10mV/sub pp/ 2/sup 31/-1 pseudo random bit sequence, a bit error rate of 5/spl middot/10/sup -12/ at 3.5Gbit/s has been measured. At lower bitrates the bit error rate is even lower: a 1 Gbit/s 10mV/sub pp/, input signal results in a bit error rate of 7/spl middot/10/sup -14/. The rms jitter is 12ps. The postamplifier circuit consumes only 19mA from a 1.8V power supply.