Notice of Violation of IEEE Publication PrinciplesA 12.5GHz SiGe BICMOS limiting amplifier using a dual offset cancellation loop

A 12.5GHz limiting amplifier was realized in a 0.2μm 90GHz f/sub T/ SiGe BICMOS process. The signal path was implemented as a cascade of emitter followers and differential stages using multiple capacitive peaking networks. The output offset voltage was reduced to fractions of mV by using a dual active offset cancellation loop having the compensation capacitance integrated on-chip due to a Miller multiplication architecture. ICs specifications include: >60dB signal path gain, <0.2mV output offset voltage, >12.5GHz signal path bandwidth, 1mV input sensitivity, <25ps rise/ fall time, <15ps deterministic jitter, 1.5×1.5mm/sup 2/ die area and 25mA current from a 3.3V 7±10% supply voltage.