3.5Gbit/s后置放大器，0.18/spl mu/m CMOS

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI:10.1109/ESSCIR.2005.1541652

C. Hermans, M. Steyaert

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引用次数: 4

摘要

提出了一种采用标准的0.18/spl mu/m 1.8V CMOS技术实现的带输出缓冲器的后置放大器。后置放大器和输出缓冲器均采用宽带技术，实现了高速运算。对于差分10mV/sub / pp/ 2/sup 31/-1伪随机比特序列，在3.5Gbit/s时测量到5/spl middot/10/sup -12/的误码率。在较低的比特率下，误码率甚至更低:1 Gbit/s 10mV/sub / pp/，输入信号的误码率为7/spl / middot/10/sup -14/。有效值抖动是12ps。后置放大电路从1.8V电源中仅消耗19mA。

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A 3.5Gbit/s post-amplifier in 0.18/spl mu/m CMOS

A postamplifier with output buffer implemented in a standard 0.18/spl mu/m 1.8V CMOS technology is proposed. Using broadband techniques for both postamplifier and output buffer, highspeed operation has been achieved. For a differential 10mV/sub pp/ 2/sup 31/-1 pseudo random bit sequence, a bit error rate of 5/spl middot/10/sup -12/ at 3.5Gbit/s has been measured. At lower bitrates the bit error rate is even lower: a 1 Gbit/s 10mV/sub pp/, input signal results in a bit error rate of 7/spl middot/10/sup -14/. The rms jitter is 12ps. The postamplifier circuit consumes only 19mA from a 1.8V power supply.

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Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.

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