内置I/sub DDQ/测试电路

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI:10.1109/ESSCIR.2005.1541662

S. Matakias, Y. Tsiatouhas, A. Arapoyanni, T. Haniotakis, G. Prenat, S. Mir

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引用次数: 1

摘要

虽然I/sub DDQ/测试已成为一种被广泛接受的CMOS缺陷检测技术，但其在极深亚微米技术中的有效性受到晶体管泄漏电流增加的威胁。本文提出了一个内置的I/sub DDQ/测试电路，旨在扩展I/sub DDQ/测试在未来技术中的可行性，并讨论了初步实验结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A built-in I/sub DDQ/ testing circuit

Although I/sub DDQ/ testing has become a widely accepted defect detection technique for CMOS ICs, its effectiveness in very deep submicron technologies is threatened by the increased transistor leakage current. In this paper, a built-in I/sub DDQ/ testing circuit is presented, that aims to extend the viability of I/sub DDQ/ testing in future technologies and first experimental results are discussed.

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Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.

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