A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18/spl mu/m digital CMOS technology

Abstract

This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying the required specifications for short-haul receivers. Implemented in a 0.18/spl mu/m digital CMOS technology, total power dissipation is 70.2mW or 3.51mW/Gbps/ch and each channel occupies 0.045/spl mu/m/sup 2/ silicon area.