B. Pellat, J. Blanc, F. Goussin, D. Thevenet, Sandrine Majcherczak, F. Reaute, D. Belot, P. Garcia, P. Persechini, Patrick Cerisier, P. Conti, P. Level, M. Kraemer, A. Granata
{"title":"Fully-integrated WCDMA SiGeC BiCMOS transceiver","authors":"B. Pellat, J. Blanc, F. Goussin, D. Thevenet, Sandrine Majcherczak, F. Reaute, D. Belot, P. Garcia, P. Persechini, Patrick Cerisier, P. Conti, P. Level, M. Kraemer, A. Granata","doi":"10.1109/ESSCIR.2005.1541674","DOIUrl":null,"url":null,"abstract":"This paper describes a WCDMA transceiver integrated and in a SiGe-C 0.25um BiCMOS process featuring Ft=60GHz bipolar transistor. The receiver part includes integrated zero-IF RF-Front-End. The transmitter is based on Variable IF architecture and includes a 64 dB gain control. All required PLL's and associated VCO's are also integrated. The receiver power consumption is 37mA (PLL included) and the transmitter consumes 60mA both under 2.7V power supply generated by an internal low drop regulator (LDO) directly connected to the battery voltage. Within the receive band, the receiver measurements shown 64dB of overall gain with a 5 dB NF DSB. The transmitter maximum output power is -3 dBm.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIR.2005.1541674","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This paper describes a WCDMA transceiver integrated and in a SiGe-C 0.25um BiCMOS process featuring Ft=60GHz bipolar transistor. The receiver part includes integrated zero-IF RF-Front-End. The transmitter is based on Variable IF architecture and includes a 64 dB gain control. All required PLL's and associated VCO's are also integrated. The receiver power consumption is 37mA (PLL included) and the transmitter consumes 60mA both under 2.7V power supply generated by an internal low drop regulator (LDO) directly connected to the battery voltage. Within the receive band, the receiver measurements shown 64dB of overall gain with a 5 dB NF DSB. The transmitter maximum output power is -3 dBm.