{"title":"Design Flow to Develop Wideband Inverter-Based Circuits Using C/ID Methodology","authors":"Behdad Jamadi, Fariborz T. Ordubadi, A. Tajalli","doi":"10.1109/SMACD58065.2023.10192184","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192184","url":null,"abstract":"A systematic design flow based on C/ID methodology for developing high-speed inverter-based amplifiers will be proposed, with the goal to minimize design iterations and maintain high precision. This methodology enables designers to select the most energy- and power-efficient amplifier topology based on target requirements, especially operating speed. For this study, an established CMOS 28 nm technology is utilized, wherein, the performance of inverter-based amplifiers is compared against the conventional continuous-time differential amplifier topologies, i.e., differential PFET and NFET Current-Mode Logic (CML) circuits. The proposed design methodology shows less than ± 5% mismatch to the transistor-level simulations.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124870651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
David Bierbuesse, F. Dietrich, Eduard Heidebrecht, R. Negra
{"title":"Circuit Synthesis of a 140–220 GHz Low-Noise Amplifier in 130 nm SiGe BiCMOS","authors":"David Bierbuesse, F. Dietrich, Eduard Heidebrecht, R. Negra","doi":"10.1109/SMACD58065.2023.10192183","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192183","url":null,"abstract":"The synthesis of a broadband LNA operating at THz-frequencies is presented. The overall synthesis time does not exceed 2.5 hours. To the best of the author’s knowledge, this work presents the first ever published synthesis of a THz LNA circuit. The synthesized LNA provides more than 15 dB gain over a frequency range from 140–220 GHz with a 3dB-bandwidth of 70 GHz from 150–220 GHz. The minimum noise figure is 8.2 dB and a maximum P1dB of −1.5 dBm can be achieved in simulation.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115200494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. van Rijs, İlke Ercan, A. Vladimirescu, F. Sebastiano
{"title":"Single-Electron-Transistor Compact Model for Spin-Qubit Readout","authors":"S. van Rijs, İlke Ercan, A. Vladimirescu, F. Sebastiano","doi":"10.1109/SMACD58065.2023.10192251","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192251","url":null,"abstract":"Quantum computers process information stored in quantum bits (qubits), which must be controlled and read out by a traditional electronic interface. Co-designing and cooptimizing such a quantum-classical complex system requires efficient simulators to emulate the qubits and their interaction with classical electronics. For spin-qubit readout, a single electron transistor (SET) is often employed. To build a toolset that can co-simulate the spin qubit system with the classical control and readout interface, a compact and efficient SET model is needed. This paper presents a new compact empirical SET model based on state-of-the-art SET measurement and extracted by a custom function-fitting python program. Within the target source-drain voltage range of ±1000μV , the model is accurate for circuit (SPICE) simulation. Furthermore, the empirical model is represented by a set of equations that enables instantaneous output response requiring a negligible simulation time. With this new SET model, a quantum-electronics co-simulator such as SPINE can now be enhanced to simulate the readout in addition to the control circuits of spin qubits, thus enabling the design of the complete integrated circuit (IC) required for large-scale quantum computers.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128553886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tugçe Ayraç, Anıl Özdemirli, Emre Apaydin, Kemal Ozanoglu, M. Yazgi
{"title":"Comparative Evaluation of Multiline TRL and 2X-Thru De-Embedding Implementation Methods on Printed Circuit Board Measurements","authors":"Tugçe Ayraç, Anıl Özdemirli, Emre Apaydin, Kemal Ozanoglu, M. Yazgi","doi":"10.1109/SMACD58065.2023.10192140","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192140","url":null,"abstract":"This work presents a comprehensive study of two different de-embedding techniques: the Multiline method and the 2X-Thru fixture removal. The methods are compared in terms of calibration standard requirements, de-embedding methodology, fixture removing accuracy, and de-embedding results. The comparison reveals that the accuracy of the Multiline method strictly depends on the impedance variation between calibration standards. The 2X-Thru with impedance correction, on the other hand, is more prone to impedance variation since it relies on a single calibration standard, which also eases the measurement routine and reduces the complexity. One important aim of this study is to contribute to the development of open-source de-embedding tools since the validity and accuracy of commercial tools cannot be evaluated for academic purposes.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129622401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Stability Analysis for Frequency Tunable Bandpass Delta-Sigma ADC Architectures","authors":"Jesko Flemming, B. Wicht, Pascal Witte","doi":"10.1109/SMACD58065.2023.10192145","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192145","url":null,"abstract":"This paper presents bandpass delta-sigma modulator (BP-Δ∑M) structures, which are specifically suited for frequency tuning. The structures are identified through stability analyses and comparisons between chain of resonators feedforward (CRFF) and chain of resonators feedback (CRFB) delta-sigma modulator (Δ∑M) configurations. Frequency tuning is predominantly achieved through altering the resonator coefficients. Therefore, the paper guides designers though the analysis process for identifying suitable tunable BP-Δ∑M structures. When moderately changing the resonators the structures perform almost identical to a non-tunable modulator optimized for the same frequency. For large frequency shifts, the out-of-band gain (OOBG) of the signal transfer function (STF) and noise transfer function (NTF) in the CRFF structure, drastically increases and the control loop becomes unstable. It is shown how utilizing CRFB structures is advantageous for frequency tuning and that the OOBG in CRFF structures can be compensated through a unity STF (USTF) Δ∑M structure.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124050921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Jitter Modeling for High Precision Frequency Measurements in Oscillator Circuits","authors":"Utku Arda Akinci, Muhammed Salih Inneci, Zeynep Duygu Sütgöl, Faik Baskaya, Günhan Dündar","doi":"10.1109/SMACD58065.2023.10192248","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192248","url":null,"abstract":"This paper studies the concept of jitter in a frequency measurement system and proposes a method of converting phase noise to random jitter. The study illustrates the impact of jitter on a PLL circuit by constructing a model of an oscillator with realistic random jitter. The modeled jitter was implemented using Verilog, and the outcomes were examined using MATLAB. We present a comprehensive approach to generate jitter via a phase noise model, which simplifies the testing of circuits under different conditions, such as various environments and temperatures. To verify the proposed method, the simulations of a 1st order Bang-Bang Phase Locked Loop Frequency-to-Digital Converter are performed with and without jitter. The results indicate that the proposed method of converting phase noise to random jitter provides an accurate and reliable way to examine the robustness of circuits under the presence of jitter.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133889121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modelling and Optimization of a Mixed-Signal Accelerator for Deep Neural Networks","authors":"Michele Caselli, A. Boni","doi":"10.1109/SMACD58065.2023.10192111","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192111","url":null,"abstract":"This paper proposes an analytical model for the optimized circuit design in an SRAM-based mixed-signal accelerator for Deep Neural Networks. The model, includes fundamental non-idealities to maintain the information content of the MAC operation, and it exploits a statistical approach to generates specification for the memory accelerator. In a case of study, the model optimization carried out with MATLAB allows to avoid three bits of ADC over-design, with large area and energy savings.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127663095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lomash Chandra Acharya, Anubhav Kumar, Khoirom Johnson Singh, Neha Gupta, Nayakanti Sai Shabarish, Neeraj Mishra, Mahipal Dargupally, A. Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, S. Dasgupta, B. Anand
{"title":"Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure","authors":"Lomash Chandra Acharya, Anubhav Kumar, Khoirom Johnson Singh, Neha Gupta, Nayakanti Sai Shabarish, Neeraj Mishra, Mahipal Dargupally, A. Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, S. Dasgupta, B. Anand","doi":"10.1109/SMACD58065.2023.10192158","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192158","url":null,"abstract":"This article proposes a method for performing device-level variability-aware static timing analysis (STA) on digital circuits using a tool flow methodology based on Python and Bash scripting. The method involves creating an effective current source model (ECSM) .libs file with a custom tool flow, which incorporates variation-aware timing models of standard cells to minimize recharacterization efforts. The resulting file is integrated into an industry-standard STA tool environment to assess the impact of device and layout level variability on digital timing closure. The simulation work is carried out using Mentor Graphics ELDO SPICE, Synopsys DC Compiler, and PrimeTime STA environment in STMicroelectronics (STM) 65 nm CMOS process. This tool flow reduces recharacterization efforts by 98.13% compared to conventional SPICE simulation by incorporating the impact of device-level variability on the conventional STA flow.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123304220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Olympia Axelou, Eleni Tselepi, G. Floros, N. Evmorfopoulos, G. Stamoulis
{"title":"PROTON – A Python Framework for Physics-Based Electromigration Assessment on Contemporary VLSI Power Grids","authors":"Olympia Axelou, Eleni Tselepi, G. Floros, N. Evmorfopoulos, G. Stamoulis","doi":"10.1109/SMACD58065.2023.10192229","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192229","url":null,"abstract":"Electromigration (EM) is a significant reliability concern in modern circuit design practices that poses a considerable risk to the long-term reliability of contemporary integrated circuits and attracts attention from the EDA industry. Hence, the development of a robust, industrial-level EM analysis tool is crucial. In order to address this challenge, we present PROTON, an open-source tool that can be straightforwardly integrated into industrial design flows covering a wide spectrum of EM analysis needs. On top of this, it offers an intuitive graphical user interface with a high level of automation that allows the visualization of EM stress analysis on power grid designs. The core of PROTON incorporates state-of-the-art methodologies for physics-based EM stress analysis which provide robustness and scalability in handling large-scale power grid designs. These are experimentally verified in comparison with the industrial tool COMSOL on multiple benchmarks where PROTON demonstrated a speedup of ×685 with negligible loss in accuracy.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124493059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Christoph W. Wagner, Niklas Bräunlich, Kevin E. Drenkhahn, Georg Gläser
{"title":"Shut Off! – Hybrid BICMOS Logic for Power-Efficient High Speed Circuits","authors":"Christoph W. Wagner, Niklas Bräunlich, Kevin E. Drenkhahn, Georg Gläser","doi":"10.1109/SMACD58065.2023.10192217","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192217","url":null,"abstract":"Power efficiency is crucial, especially in high-speed systems, where conventional approaches like clock gating cannot be employed readily. Special logic families, such as Positive Emitter-Coupled Logic (PECL), push the technological frontier, promising even more speed at the expense of an even more strained power budget. We propose a novel hybrid of PECL and Complementary Metal-Oxide-Semiconductor (CMOS) logic to introduce Function Shut-off (FSO), realizing a shut-off at the level of functional blocks and logic primitives inside complex logic cells. Using this approach, we realize a high-speed Linear Feedback Shift Register (LFSR) in a SiGe technology, extending the State of the Art (SOTA) by adding reconfigurability, which is required for its use as sequence generator in Compressed Sensing (CS) applications. We present measurements showing successful fabrication and performance of the packaged die at 20.4 GHz. In this LFSR, employing FSO reduces the supply current by a factor of up to four (depending on the chosen configuration) and reduces active area by 17%.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122869057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}