超越SPICE仿真:一种用于数字时序关闭的新型可变性感知STA方法

Lomash Chandra Acharya, Anubhav Kumar, Khoirom Johnson Singh, Neha Gupta, Nayakanti Sai Shabarish, Neeraj Mishra, Mahipal Dargupally, A. Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, S. Dasgupta, B. Anand
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引用次数: 0

摘要

本文提出了一种在数字电路上使用基于Python和Bash脚本的工具流方法执行设备级可变感知静态时序分析(STA)的方法。该方法包括使用自定义工具流创建一个有效的电流源模型(ECSM) .lib文件,该文件包含了标准单元的变化感知时序模型,以最大限度地减少重新表征的工作量。生成的文件集成到行业标准的STA工具环境中,以评估设备和布局级别变化对数字定时关闭的影响。仿真工作采用Mentor Graphics ELDO SPICE、Synopsys DC Compiler和PrimeTime STA环境在STMicroelectronics (STM) 65nm CMOS工艺中进行。与传统的SPICE模拟相比,该工具流通过结合设备级可变性对传统STA流的影响,减少了98.13%的重新表征工作。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure
This article proposes a method for performing device-level variability-aware static timing analysis (STA) on digital circuits using a tool flow methodology based on Python and Bash scripting. The method involves creating an effective current source model (ECSM) .libs file with a custom tool flow, which incorporates variation-aware timing models of standard cells to minimize recharacterization efforts. The resulting file is integrated into an industry-standard STA tool environment to assess the impact of device and layout level variability on digital timing closure. The simulation work is carried out using Mentor Graphics ELDO SPICE, Synopsys DC Compiler, and PrimeTime STA environment in STMicroelectronics (STM) 65 nm CMOS process. This tool flow reduces recharacterization efforts by 98.13% compared to conventional SPICE simulation by incorporating the impact of device-level variability on the conventional STA flow.
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