2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)最新文献

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Application of New Metal-Oxide Memristor Models in Digital and Analog Electronic Circuits 新型金属氧化物忆阻器模型在数字和模拟电路中的应用
S. Kirilov, V. Mladenov
{"title":"Application of New Metal-Oxide Memristor Models in Digital and Analog Electronic Circuits","authors":"S. Kirilov, V. Mladenov","doi":"10.1109/SMACD58065.2023.10192136","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192136","url":null,"abstract":"Memristors, as novel nonlinear electronic components are under intensive analyses, owing to their excellent switching and memory properties, low power usage, nano-sizes, and good compatibility to traditional CMOS integrated chips. They are applicable in electronic schemes, incorporated in chips. Engineering of memristor circuits presents opportunities for design of chips with ultra-high density and many applications. In the last years, several modified and enhanced memristor models, built on the frequently used standard models are proposed. They are simplified, with a good accuracy and high operating rate. The aim of this paper is to present the applicability of the enhanced models in electronic schemes and a comparison of their properties and performance in LTSPICE environment. Several schemes, as memory crossbars, logic gates, neural nets, and various reconfigurable circuits are analyzed. The modified memristor models are compared to various standard models, according to different criteria, as operating frequency, precision, simulation time, switching properties and complexity. The major advantages of the improved models are represented – fast operation, good convergence, accuracy, and applicability in complex electronic devices and circuits.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123271077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Procedural Generator for the Sizing and Physical Synthesis of a MOSFET Low-Side Driver 用于MOSFET低侧驱动器尺寸和物理合成的程序生成器
David Demiri, G. Capodivacca, Daniele Privato, Husni M. Habal, Florian Renneke
{"title":"A Procedural Generator for the Sizing and Physical Synthesis of a MOSFET Low-Side Driver","authors":"David Demiri, G. Capodivacca, Daniele Privato, Husni M. Habal, Florian Renneke","doi":"10.1109/SMACD58065.2023.10192153","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192153","url":null,"abstract":"A flow is presented to build procedural generators for analog integrated circuits at the transistor level. It includes procedural schematic sizing, design centering, layout generation, and post-layout verification. The procedures for front and backend generation are jointly constructed to make use of the same set of design parameters and geometric constraints. The flow is used to write a generator for the MOSFET low-side driver of a dcdc boost converter. Physical layout area, electrical performance, and design effort are comparable to the results of a conventional manual design of the same circuit. The real benefit is in generator reuse following changes in the specifications or technology.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127595709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Under Cover: On-FPGA Coverage Monitoring by Netlist Instrumentation 下表:Netlist Instrumentation的fpga覆盖监控
Manuel Jirsak, Henning Siemen, Jonas Lienke, Martin Grabmann, Eric Schäfer, Georg Gläser
{"title":"Under Cover: On-FPGA Coverage Monitoring by Netlist Instrumentation","authors":"Manuel Jirsak, Henning Siemen, Jonas Lienke, Martin Grabmann, Eric Schäfer, Georg Gläser","doi":"10.1109/SMACD58065.2023.10192205","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192205","url":null,"abstract":"Verifying a digital circuit design by using an FPGA-based emulation has the advantage that it can be tested in a realistic environment, for instance, with an attached analog frontend. Besides this, the emulation is typically faster than a hardware simulation. However, it is not feasible to retrieve any coverage information from an FPGA, as it is possible with a simulation. We present a method for instrumenting a design with synthesizable coverage monitors that enable proper coverage readout when using FPGA prototypes. We showcase our method on a UHF RFID based smart sensor interface with about 3600 flip-flops and demonstrate the instrumentation process and coverage readout. This allows verification and firmware engineers to run test cases with an FPGA-based emulation and also rely on standard metrics for test coverage.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126782570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Wide-Band Shared LNA for Large Scale Neural Recording Applications 大规模神经记录应用的宽带共享LNA
Alessandro Fava, F. Centurelli, Andrea Vittimberga, G. Scotti
{"title":"Wide-Band Shared LNA for Large Scale Neural Recording Applications","authors":"Alessandro Fava, F. Centurelli, Andrea Vittimberga, G. Scotti","doi":"10.1109/SMACD58065.2023.10192164","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192164","url":null,"abstract":"Optimizing the LNA front-end of a neural recording channel for noise allows achieving a bandwidth that can be exploited to interface several electrodes in a frequency-division multiplexing approach, resulting in an optimization of power and area consumption for the overall neural recording system. This paper presents a wide-band LNA front-end whose bandwidth is maximized for the given noise level, so that it can be shared among different electrodes. The resulting architecture achieves a remarkable NEF value, as demonstrated by the simulations performed in a commercial 130nm CMOS technology.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128570331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-Gm CMOS Transconductors with Wide Tuning Range for Bioimpedance Spectroscopy 生物阻抗光谱宽调谐范围的低gm CMOS传感器
Israel Corbacho, J. M. Carrillo, J. L. Ausín, M. A. Domínguez, R. Pérez-Aloe, J. F. Duque-Carrillo
{"title":"Low-Gm CMOS Transconductors with Wide Tuning Range for Bioimpedance Spectroscopy","authors":"Israel Corbacho, J. M. Carrillo, J. L. Ausín, M. A. Domínguez, R. Pérez-Aloe, J. F. Duque-Carrillo","doi":"10.1109/SMACD58065.2023.10192142","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192142","url":null,"abstract":"Two techniques to design a low-transconductance (Gm) widely-tunable transconductor are described. The operation principle consists in both cases in the subtraction of two nominally equal transconductances, one of which can be electronically tuned. The circuit implementation differs, being one solution based on the use of source followers (SF), a linearization resistor, and a tunable current mirror, and consisting the other approach of differential pairs (DP) with resistive source degeneration, and an electronically programmable current biasing. Both transconductors have been designed in 180 nm CMOS technology to operate with 1.8 V. The SF and DP solutions achieve a minimum Gm nominal value of 1.38 nA/V and 6.03 nA/V, respectively, with a simulated transconductance tuning range of 729.6× and 7129.4×, also respectively, obtained from a Montecarlo analysis. The application of the transconductors to the design of a second-order Gm − C bandpass filter for signals separation in multi-sine bioimpedance spectroscopy is also addressed.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127154076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design Strategies to Select the Best Locations in a Ring Oscillator PUF 环形振荡器PUF中最佳位置选择的设计策略
Raúl Aparicio-Téllez, M. Garcia-Bosque, Guillermo Díez-Señorans, C. Sánchez-Azqueta, S. Celma
{"title":"Design Strategies to Select the Best Locations in a Ring Oscillator PUF","authors":"Raúl Aparicio-Téllez, M. Garcia-Bosque, Guillermo Díez-Señorans, C. Sánchez-Azqueta, S. Celma","doi":"10.1109/SMACD58065.2023.10192224","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192224","url":null,"abstract":"This work analyzes the frequencies of identical ring oscillators across several locations and FPGAs. Based on this analysis, a new strategy to select the locations of the oscillators in a ring oscillator PUF has been proposed. Finally, using novel figures of merit, this work evaluates the impact of this strategy, showing that it can greatly improve the uniqueness of any ring oscillator PUF of compensated measurement while maintaining approximately the same reproducibility.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121605317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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