Atakan Türker, Kemal Ozanoglu, Engin Afacan, Günhan Dündar
{"title":"Analysis of SAR ADC Performance Under Radiation Exposure","authors":"Atakan Türker, Kemal Ozanoglu, Engin Afacan, Günhan Dündar","doi":"10.1109/SMACD58065.2023.10192128","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192128","url":null,"abstract":"This paper investigates the radiation effects on Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) for space applications. Total Ionizing Dose (TID) and Single Event Transient (SET) are considered for two types of SAR ADCs: split capacitor array Digital-to-Analog Converter (DAC) based and C-2C ladder-based DAC based. The effect of TID is modeled as the offset change in the comparator, while the SET effect is simulated through applying instant currents to different nodes on the DACs. According to the simulation results, TID causes missing codes, whereas SET may cause bit flips in the output code depending on the incident time and the location of the SET event. Also, it is observed that the SET performance of the SAR ADC with split capacitor array DAC is better with respect to the C-2C ladder-based DAC. The performed analysis provides valuable circuit design insights to achieve radiation-hardened SAR ADCs.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121024128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Atif Yasin, Tiankai Su, S. Pillement, M. Ciesielski
{"title":"Formal Verification of Divider Circuits by Hardware Reduction","authors":"Atif Yasin, Tiankai Su, S. Pillement, M. Ciesielski","doi":"10.1109/SMACD58065.2023.10192137","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192137","url":null,"abstract":"The paper introduces a novel verification method of gate-level hardware implementation of divider circuits. The method, called hardware reduction, accomplishes the verification by appending the divider circuit with another circuit, which implements its arithmetic inverse, followed by logic synthesis. If the circuit under verification is correct, the resulting resynthesized circuit becomes trivially redundant (composed of wires or buffers only). This method outperforms the established Boolean satisfiability, SAT-based and equivalence checking techniques and does not require a reference design.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129694836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kerem Kaya, Kemal Ozanoglu, Y. Kahya, Günhan Dündar
{"title":"Programmable Switched-Capacitor Filter Design Tool for Biomedical Signal Acquisition","authors":"Kerem Kaya, Kemal Ozanoglu, Y. Kahya, Günhan Dündar","doi":"10.1109/SMACD58065.2023.10192182","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192182","url":null,"abstract":"This paper presents an open source design support tool for a respiratory and cardiac signal acquisition system that utilizes programmable switched-capacitor analog filters in the analog front end. The proposed filter topologies are based on cascaded second-order-section filters and are designed to be programmable in terms of the cut-off frequency via the switching frequency. The design support tool is written in Python and is capable of calculating the capacitance ratios for a given second-order filter topology, generating a parameter file, and performing periodic AC simulations of the designed circuit in SpectreRF. The tool uses a simple estimation algorithm to find the best possible integer fit with an error cost function. Two sets of 6th-order switched-capacitor filter sets are designed using biquadratic sections in 180nm CMOS process. The proposed design methodology offers a better area fraction reduction compared to simple integer ratio designs. Post-layout simulation results demonstrate the effectiveness and efficiency of the proposed design support tool for switched-capacitor analog filters in respiratory and cardiac signal acquisition systems.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129695776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Uniformity Adjustment of Delay-Based Physical Unclonable Function: Modeling and Analysis","authors":"Hadis Takaloo, Mehdi Ahmadi, A. Ahmadi","doi":"10.1109/SMACD58065.2023.10192237","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192237","url":null,"abstract":"We discuss a theoretical model to evaluate the source of entropy from a mathematical point of view targeting optimized intrinsic security mechanisms implemented by Physical Unclonable Functions (PUFs). The results develop a profitable design tool that can address the most crucial model parameters suitable to adjust the system uniformity without imposing additional electronic gates. The study pursues the theoretical approach by a low-complexity CMOS circuit solution implementing the mathematical models aiming at proposing methodical approaches for implementing security mechanisms embedded in hardware.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125898862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Pasadas, A. Pacheco-Sánchez, N. Mavredakis, D. Jiménez
{"title":"Graphene field-effect transistor TCAD tool for circuit design under freeware","authors":"F. Pasadas, A. Pacheco-Sánchez, N. Mavredakis, D. Jiménez","doi":"10.1109/SMACD58065.2023.10192189","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192189","url":null,"abstract":"We present a physics-based compact model of graphene field-effect transistors (GFETs) able to be run under the freeware Quite Universal Circuit Simulator (QUCS), bringing the possibility to any user to undertake circuit simulations based on the emergent graphene technology. The model is based on the drift-diffusion mechanism for the carrier transport coupled with the solution of the electrostatics of the device structure. Simulations on QUCS of an exemplary application consisting of a GFET-based gas sensor are shown, bringing to light the potential of the technology computer-aided design (TCAD) tool developed for novel concepts of applications based on the inherent features of graphene and related materials.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124390777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
André Amaral, António Gusmão, Rafael Vieira, R. Martins, N. Horta, N. Lourenço
{"title":"An ANN-Based Approach to the Modelling and Simulation of Analogue Circuits","authors":"André Amaral, António Gusmão, Rafael Vieira, R. Martins, N. Horta, N. Lourenço","doi":"10.1109/SMACD58065.2023.10192134","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192134","url":null,"abstract":"This paper explores the automatic creation of behavioural models of analogue circuits from simulation data. Artificial neural networks (ANNs) are used to model the circuit, speeding up the simulations and providing residual error results when compared with an off-the-shelf simulator. Since the pair input-output is generated through SPICE simulation, the model is trained in a supervised manner. This work proposes to model the circuit behaviour using a multilayer perceptron with delay lines. As a novelty, it introduces an approach that can model the circuit behaviour for different circuit sizes. The proposed method was applied to a set of amplifiers and the results obtained show the effectiveness of the model in behavioural modelling of analogue circuits. A generator capable of converting the Python ANN to Verilog-A was also developed and used to convert the model from Python to this hardware description language, so that the models are ready to be integrated with the circuit simulator. Simulating the circuit using the developed models was 5 times faster than simulating it at the transistor level.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131260349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Aleksi Korsman, Verneri Hirvonen, Otto Simola, Antti Tarkka, M. Kosunen, J. Ryynänen
{"title":"End-to-End Multi-Target Verification Environment for a RISC-V Microprocessor","authors":"Aleksi Korsman, Verneri Hirvonen, Otto Simola, Antti Tarkka, M. Kosunen, J. Ryynänen","doi":"10.1109/SMACD58065.2023.10192249","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192249","url":null,"abstract":"In this paper, we present the end-to-end verification environment developed for verifying A-Core, a custom, extensible and configurable RISC-V microprocessor targeted for controlling communication, cryptography, and machine learning hardware accelerators. The developed open source verification environment utilizes a Python-based ASIC-generic system verification framework. In the developed environment, the processor can be verified with self-checking user-written Assembly- or C-programs, providing a seamless from-C-to-hardware verification methodology. With the presented test platform, test programs can be run on various targets: RTL simulation, FPGA, or ASIC, providing one verification environment for all maturity levels of the design. The platform enables end-to-end testing: verification of the functionality of the A-Core ASIC from the programming sequence over a JTAG interface to printouts over UART, providing tests coverage also for real use cases of the hardware. Performance metrics for different sized test programs are provided to enable characterization of the speed of verification.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134390796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Maximum Output Power Point Tracking for Low Power Photovoltaic Energy Harvesting Systems","authors":"L. Vicente-García, Ó. Pereira-Rial, P. López","doi":"10.1109/SMACD58065.2023.10192228","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192228","url":null,"abstract":"A novel approach for finding the maximum output power point of a photovoltaic energy harvesting system is proposed in this paper. It is based on maximizing the power delivered to the load taking into account the performance of the whole system in contrast to conventional approaches focused on tracking the maximum power point of the photovoltaic transducer alone. The output power tracking is performed by measuring the output voltage, which significantly simplifies the hardware complexity and consequently reduces the power consumption. A circuit implementation of the entire system is presented and validated using electrical simulations. The designed circuit is self powered and is able to successfully supply a load with voltage levels higher than 1.2V. The system achieves a peak efficiency of 80.51% when the input power is equal to 28.03 μW.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133059042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design and Implementation of a GPU-Based Digital Predistortion Linearizer for RF Power Amplifiers","authors":"Wantao Li, G. Montoro, P. Gilabert","doi":"10.1109/SMACD58065.2023.10192152","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192152","url":null,"abstract":"This paper presents an automated process for generating computationally efficient radiofrequency (RF) power amplifier (PA) behavioural models that can be used for digital-predistortion (DPD) linearization. The implementation of the DPD behavioral model is based on the personal computer (PC) architecture including recent graphical process units (GPUs) with compute unified device architecture (CUDA) cores. By utilizing the parallel computing capability, the proposed implementation can achieve high baseband throughput required by nowadays 5G new radio (NR) communications and the inherent DPD bandwidth expansion. The details of the DPD implementation will be given and the advantages and disadvantages of the GPU DPD will be discussed. Experimental results will validate the DPD implementation in a hardware-in-the-loop (HITL) environment with a system-on-chip (SoC) PA operated with a 100 MHz 5G-NR signal.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131411445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Automated Framework for Switched-Capacitor Power Amplifier Implementation Verified in 65 nm CMOS","authors":"Li-Yu Chen, D. Wentzloff","doi":"10.1109/SMACD58065.2023.10192186","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192186","url":null,"abstract":"This paper presents an automated design framework for Switched-Capacitor Power Amplifiers (SCPA). The framework automatically takes the specifications of SCPA as inputs, generates the layout of the corresponding SCPA and performs post parasitic extraction (PEX) simulation. The automation flow is implemented in Python and integrated with computer-aided design (CAD) tools. A prototype chip containing an SCPA generated from the proposed framework and an SCPA designed with the conventional custom design flow is presented and measurement results show that both SCPAs have less than 0.2dBm difference in maximum output power and less than 2.3% difference in efficiency while the proposed automation flow takes less than 2 hours.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121223236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}