Atif Yasin, Tiankai Su, S. Pillement, M. Ciesielski
{"title":"Formal Verification of Divider Circuits by Hardware Reduction","authors":"Atif Yasin, Tiankai Su, S. Pillement, M. Ciesielski","doi":"10.1109/SMACD58065.2023.10192137","DOIUrl":null,"url":null,"abstract":"The paper introduces a novel verification method of gate-level hardware implementation of divider circuits. The method, called hardware reduction, accomplishes the verification by appending the divider circuit with another circuit, which implements its arithmetic inverse, followed by logic synthesis. If the circuit under verification is correct, the resulting resynthesized circuit becomes trivially redundant (composed of wires or buffers only). This method outperforms the established Boolean satisfiability, SAT-based and equivalence checking techniques and does not require a reference design.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMACD58065.2023.10192137","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The paper introduces a novel verification method of gate-level hardware implementation of divider circuits. The method, called hardware reduction, accomplishes the verification by appending the divider circuit with another circuit, which implements its arithmetic inverse, followed by logic synthesis. If the circuit under verification is correct, the resulting resynthesized circuit becomes trivially redundant (composed of wires or buffers only). This method outperforms the established Boolean satisfiability, SAT-based and equivalence checking techniques and does not require a reference design.