Formal Verification of Divider Circuits by Hardware Reduction

Atif Yasin, Tiankai Su, S. Pillement, M. Ciesielski
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Abstract

The paper introduces a novel verification method of gate-level hardware implementation of divider circuits. The method, called hardware reduction, accomplishes the verification by appending the divider circuit with another circuit, which implements its arithmetic inverse, followed by logic synthesis. If the circuit under verification is correct, the resulting resynthesized circuit becomes trivially redundant (composed of wires or buffers only). This method outperforms the established Boolean satisfiability, SAT-based and equivalence checking techniques and does not require a reference design.
分频电路的硬件约简形式验证
介绍了一种新的分频电路门级硬件实现的验证方法。该方法称为硬件约简,通过将分频电路附加到另一个电路上,实现其算术逆,然后进行逻辑综合来完成验证。如果验证下的电路是正确的,则产生的重新合成电路变得微不足道的冗余(仅由导线或缓冲器组成)。该方法优于现有的布尔可满足性、基于sat和等价性检查技术,并且不需要参考设计。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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