Design and Implementation of a GPU-Based Digital Predistortion Linearizer for RF Power Amplifiers

This paper presents an automated process for generating computationally efficient radiofrequency (RF) power amplifier (PA) behavioural models that can be used for digital-predistortion (DPD) linearization. The implementation of the DPD behavioral model is based on the personal computer (PC) architecture including recent graphical process units (GPUs) with compute unified device architecture (CUDA) cores. By utilizing the parallel computing capability, the proposed implementation can achieve high baseband throughput required by nowadays 5G new radio (NR) communications and the inherent DPD bandwidth expansion. The details of the DPD implementation will be given and the advantages and disadvantages of the GPU DPD will be discussed. Experimental results will validate the DPD implementation in a hardware-in-the-loop (HITL) environment with a system-on-chip (SoC) PA operated with a 100 MHz 5G-NR signal.