Under Cover: On-FPGA Coverage Monitoring by Netlist Instrumentation

Abstract

Verifying a digital circuit design by using an FPGA-based emulation has the advantage that it can be tested in a realistic environment, for instance, with an attached analog frontend. Besides this, the emulation is typically faster than a hardware simulation. However, it is not feasible to retrieve any coverage information from an FPGA, as it is possible with a simulation. We present a method for instrumenting a design with synthesizable coverage monitors that enable proper coverage readout when using FPGA prototypes. We showcase our method on a UHF RFID based smart sensor interface with about 3600 flip-flops and demonstrate the instrumentation process and coverage readout. This allows verification and firmware engineers to run test cases with an FPGA-based emulation and also rely on standard metrics for test coverage.