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2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)最新文献

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Towards the Automated RF Power Amplifier Design 自动化射频功率放大器设计研究
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2023-07-03 DOI: 10.1109/SMACD58065.2023.10192148
Catarina Belchior, L. Nunes, P. Cabral, J. Pedro
{"title":"Towards the Automated RF Power Amplifier Design","authors":"Catarina Belchior, L. Nunes, P. Cabral, J. Pedro","doi":"10.1109/SMACD58065.2023.10192148","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192148","url":null,"abstract":"Despite radio frequency (RF) power amplifiers (PAs) are as old as radio communications, their design is still one of the most difficult electronic circuit design tasks. So, it certainly constitutes one of the fields in which design automation tools will face more difficulties to be launched. Nevertheless, because of the costs associated to the education of a PA design engineer, the many trials and errors required to reach an optimized solution, and its complexity – which hinders systematic design procedures – it is also a field in which design automation would have more impact. So, this work aims to be a step towards this goal. Starting from the optimization of a state-of-the-art PA topology, in which the active device is represented by an artificial neural network, the paper addresses some challenges associated to the desired PA design automation.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124017493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multitasking and Memcomputing in Memristor Cellular Nonlinear Networks: Insights into the Underlying Mechanisms 忆阻器细胞非线性网络中的多任务处理和Memcomputing:对潜在机制的洞察
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2023-07-03 DOI: 10.1109/SMACD58065.2023.10192210
I. Messaris, A. Ascoli, D. Prousalis, V. Ntinas, A. S. Demirkol, R. Tetzlaff
{"title":"Multitasking and Memcomputing in Memristor Cellular Nonlinear Networks: Insights into the Underlying Mechanisms","authors":"I. Messaris, A. Ascoli, D. Prousalis, V. Ntinas, A. S. Demirkol, R. Tetzlaff","doi":"10.1109/SMACD58065.2023.10192210","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192210","url":null,"abstract":"Memristor Cellular Nonlinear Networks (M-CNNs) represent a significant leap in computational technology compared to traditional Cellular Nonlinear Networks (CNNs), thanks to their multi-tasking and memcomputing capabilities. Recent studies have demonstrated various configurations of M-CNNs that utilize these capabilities to perform image processing tasks. This paper employs the Dynamic Route Map circuit-theoretic analysis tool to investigate the dynamic features of M-CNNs and shed light on the underlying mechanisms responsible for their ability to handle multiple tasks. The findings from this theoretical study offer valuable insights for the development of more compact and highly efficient data processing M-CNNs that possess such versatile properties.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"333 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122843816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ultra-Low Current Sensing from Femtoampere to Picoampere Range 从飞安培到皮安范围的超低电流传感
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2023-07-03 DOI: 10.1109/SMACD58065.2023.10192214
Uygar Yildiz, Eren Uzun, Kemal Ozanoglu, Günhan Dündar
{"title":"Ultra-Low Current Sensing from Femtoampere to Picoampere Range","authors":"Uygar Yildiz, Eren Uzun, Kemal Ozanoglu, Günhan Dündar","doi":"10.1109/SMACD58065.2023.10192214","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192214","url":null,"abstract":"This work proposes design steps to form a sample analog electrometer front-end for an ultra-low current sensor in a 0.18μm CMOS technology, which is able to measure from femtoampere to picoampere range. The performance of ultra-low current sensor interfaces can be significantly deteriorated by leakage and noise of the system. The presented design offers significantly lower leakage current, which is independent of the input signal and variations in design parameters such as gain and offset, compared to the conventional integrator. In addition, the input current noise of the system is reduced by controlling the closed-loop bandwidth of the proposed interface. Analysis and simulations show the correct operation for the current values from 1fA to 1pA range with 11 bits linearity, the sensitivity of 400aA, and the input-referred maximum current noise of 360aA.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126775482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reinforcement Learning for Analog Sizing Optimization 模拟规模优化的强化学习
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2023-07-03 DOI: 10.1109/SMACD58065.2023.10192204
Michel Chevalier, S. Trochut, R. Guizzetti, P. Urard, L. Labrak, John Samuel, Remy Cellier, N. Abouchi
{"title":"Reinforcement Learning for Analog Sizing Optimization","authors":"Michel Chevalier, S. Trochut, R. Guizzetti, P. Urard, L. Labrak, John Samuel, Remy Cellier, N. Abouchi","doi":"10.1109/SMACD58065.2023.10192204","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192204","url":null,"abstract":"This paper proposes a novel adaptation of Machine Learning (ML) techniques based on reinforcement learning for the resolution of analog sizing optimization problems. The paper details the proposed solution and highlights its performances using benchmark tests based on classical analog designs such as two-stages, rail-to-rail and folded-cascode amplifiers. This novel adaptation of the ML technique is used for the optimal design of analog circuits. SPICE simulations are used to verify the viability of the proposed algorithm and novel solutions. The GNN-FCNN approach is validated on a complex circuit with more than 50 devices","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134372841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multiscale modelling of MEMS based Pirani gauges 基于MEMS的皮拉尼仪表的多尺度建模
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2023-07-03 DOI: 10.1109/SMACD58065.2023.10192174
Prafullkrishna Dani, J. Franz, J. Knoch
{"title":"Multiscale modelling of MEMS based Pirani gauges","authors":"Prafullkrishna Dani, J. Franz, J. Knoch","doi":"10.1109/SMACD58065.2023.10192174","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192174","url":null,"abstract":"A multiscale modelling approach is presented for the functional simulation of MEMS based Pirani gauges. The approach describes the physical effects occurring at different geometric scales accurately without the need for computationally expensive simulations. Simulation results are compared to experimental measurements of fabricated test structures without using any correction factors.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132556169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 23.5–32.5GHz, 17dBm PSAT and 37.5% PAE Power Amplifier Synthesized Using an Automated Design Methodology 采用自动化设计方法合成了23.5-32.5GHz、17dBm PSAT和37.5% PAE功率放大器
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2023-07-03 DOI: 10.1109/SMACD58065.2023.10192226
F. Passos, N. Lourenço, L. Mendes, R. Martins, J. Vaz, N. Horta
{"title":"A 23.5–32.5GHz, 17dBm PSAT and 37.5% PAE Power Amplifier Synthesized Using an Automated Design Methodology","authors":"F. Passos, N. Lourenço, L. Mendes, R. Martins, J. Vaz, N. Horta","doi":"10.1109/SMACD58065.2023.10192226","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192226","url":null,"abstract":"The design of power amplifiers (PAs) in the millimeter-wave (mm-Wave) regime is remarkably complex. In order to meet the linearity and efficiency requirements for 5G or 6G operation, designers have been struggling to efficiently design such PAs in a reasonable time. Hence, in the past few years, a growing interest has emerged in developing optimization-based methodologies which can automatize the design of mm-Wave circuits. In this paper, a fully-automated, process, voltage and temperature (PVT), and layout-aware optimization-based design strategy is applied to the design of a mm-Wave PA. It accurately models the transformers in the PA using machine-learning techniques and exploits a multi-objective optimization algorithm, achieving a Pareto optimal front (POF) containing hundreds of PAs over the landscape of the performance trade-offs. By leveraging the layout in the loop, it outputs a set of design solutions that have their GDSII readily available and ready to fabricate without the need for further designer intervention.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115338247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
NVSystolic: Heterogeneous Simulation Framework for Emerging Memories with Systolic Array NVSystolic:基于收缩阵列的新兴记忆异构仿真框架
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2023-07-03 DOI: 10.1109/SMACD58065.2023.10192216
Chithambara Moorthii, Sufyan Khan, M. Suri
{"title":"NVSystolic: Heterogeneous Simulation Framework for Emerging Memories with Systolic Array","authors":"Chithambara Moorthii, Sufyan Khan, M. Suri","doi":"10.1109/SMACD58065.2023.10192216","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192216","url":null,"abstract":"In recent years, hardware accelerators have shown significant advantages in the field of deep neural networks. The architecture used in such systems has high memory utilization. To make the most of memory technology in conjunction with compute fabric, careful study of memory optimisation is thus necessary. NVSystolic, a heterogeneous simulation framework based on reconfigurable memory subsystems with a systolic array serving as the computing unit, is presented in this study. In particular, Non-Volatile Memory (NVM) can be modelled by the framework for the systolic array-based accelerator.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"34 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130164647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel Area Efficient Inductorless Super-Regenerative Receiver Front-End for Medical Brain Implants 一种用于医用脑植入物的新型高效无电感超再生接收器前端
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2023-07-03 DOI: 10.1109/SMACD58065.2023.10192188
Naci Pekcokguler, Günhan Dündar, C. Dehollain
{"title":"A Novel Area Efficient Inductorless Super-Regenerative Receiver Front-End for Medical Brain Implants","authors":"Naci Pekcokguler, Günhan Dündar, C. Dehollain","doi":"10.1109/SMACD58065.2023.10192188","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192188","url":null,"abstract":"A novel area and energy efficient inductorless super-regenerative receiver (SRR) is proposed for medical brain implants dedicated to epilepsy monitoring and treatment. The proposed SRR was fabricated in UMC CMOS 180nm technology. The SRR occupies only 0.072mm2 which corresponds to an order of magnitude area reduction compared to the state-of-the-art. The SRR achieves −70dBm sensitivity and the highest data rate is 4 Mbps. 3.22 nJ/b energy efficiency is obtained with 12.9mW power consumption from a 1.8V power supply.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"646 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131882277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Programmable Circuit Based on the Combination of VTM Cellular Crossbars 基于VTM蜂窝交叉棒组合的可编程电路
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2023-07-03 DOI: 10.1109/SMACD58065.2023.10192103
Farzad Mozafari, Mehdi Ahmadi, Arash Ahmadi
{"title":"A Programmable Circuit Based on the Combination of VTM Cellular Crossbars","authors":"Farzad Mozafari, Mehdi Ahmadi, Arash Ahmadi","doi":"10.1109/SMACD58065.2023.10192103","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192103","url":null,"abstract":"This paper proposes a design of a programmable circuit based on the combination of crossbar arrays using the VTM-NAND/AND logic gates. The novelty of this work is the utilization pipeline technique for the proposed arrangements. The important feature of this method is multiple instructions overlap during execution where designed cells will never be idle, that causes an increase in the number of instructions executed simultaneously and speed of calculations. All of the digital gates and proposed circuits are evaluated using an advanced memristor model with a modified Biolek window and a voltage-dependent variable exponent.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133980463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
PyXEL: Exploring Bitstream Analysis to Assess and Enhance the Robustness of Designs on FPGAs PyXEL:探索位流分析以评估和增强fpga设计的稳健性
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2023-07-03 DOI: 10.1109/SMACD58065.2023.10192116
C. D. Sio, S. Azimi, L. Sterpone, D. M. Codinachs, F. Decuzzi
{"title":"PyXEL: Exploring Bitstream Analysis to Assess and Enhance the Robustness of Designs on FPGAs","authors":"C. D. Sio, S. Azimi, L. Sterpone, D. M. Codinachs, F. Decuzzi","doi":"10.1109/SMACD58065.2023.10192116","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192116","url":null,"abstract":"Commercial hardware-reconfigurable systems-on-chip are highly attractive for mission-critical applications in the space and automotive industries. However, their vulnerability to soft errors is a major concern, and analyzing the robustness of these systems is a complex task due to the lack of dedicated tools, information, and methodologies available. PyXEL is a tool designed to address these issues, providing the methodology for automating reliability analysis based on radiation and fault injection campaigns and facilitating the development of mitigation solutions based on customized place-and-route. Furthermore, PyXEL offers the methodology for visualizing, decoding, and analyzing the configuration data of programmable hardware devices, enabling more precise and efficient evaluation and analysis of the robustness of systems implemented on programmable hardware devices.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"55 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114047049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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