David Bierbuesse, F. Dietrich, Eduard Heidebrecht, R. Negra
{"title":"RapidIP - Fast & Universal Synthesis of RF-Circuits","authors":"David Bierbuesse, F. Dietrich, Eduard Heidebrecht, R. Negra","doi":"10.1109/SMACD58065.2023.10192113","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192113","url":null,"abstract":"A fast and universal approach of complex RF-circuit synthesis is presented. By means of generic design algorithms and efficient methods of circuit analysis, thousands of different circuit topologies can be evaluated and optimized within minutes. Universality is demonstrated by the synthesis of 4 RF-power amplifiers in 150 nm GaN and 130 nm SiGe for the operation in the 17 GHz to 21 GHz and 180 GHz to 220 GHz frequency band. The power amplifiers show competitive large signal performance in terms of gain and power-added efficiency with up to 38%. The required synthesis runtime does not exceed 22 minutes.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116322234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Alptekin Vardar, Li Zhang, Saiyam Bherulal Jain, Shaown Mojumder, N. Laleni, S. De, T. Kämpfe
{"title":"The True Cost of Errors in Emerging Memory Devices: A Worst-Case Analysis of Device Errors in IMC for Safety-Critical Applications","authors":"Alptekin Vardar, Li Zhang, Saiyam Bherulal Jain, Shaown Mojumder, N. Laleni, S. De, T. Kämpfe","doi":"10.1109/SMACD58065.2023.10192126","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192126","url":null,"abstract":"In-memory computing devices are prone to errors that can significantly affect the accuracy of neural network inference. While average accuracy loss is often used to evaluate the impact of such errors, this metric may not be reliable for safety-critical systems where worst-case performance is crucial. In this work, we present a comprehensive statistical analysis of the variability in the accuracy of quantized neural networks. We conduct experiments on two well-known neural network architectures, LeNet-5 and ResNet20, using both 4-bit and 8- bit quantization, and measure the worst-case impact of errors on model accuracy. Our results demonstrate that worst-case variation is much more significant than the impact on average accuracy and that 8-bit quantization is more susceptible to errors. We also investigate the potential of intra-layer mixed error injection to mitigate the effects of errors and show that it can improve the worst-case accuracy of neural networks.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"617 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116327810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Design Methodology of MMIC Power Amplifiers Using AI-driven Design Techniques","authors":"Liyuan Xue, Haijun Fan, Yuan Ding, Bo Liu","doi":"10.1109/SMACD58065.2023.10192155","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192155","url":null,"abstract":"Designing a monolithic microwave integrated circuit (MMIC) power amplifier (PA) is challenging due to the involvement of multiple stages with tens of parameters and several types of simulations. To address this challenge, artificial intelligence (AI) techniques have gained significant attention. This paper presents an AI-driven design methodology for MMIC PAs, which incorporates a surrogate model-assisted global optimization algorithm, data-flow interface, and simulators. The proposed methodology is verified on a practical 3-stage PA design case that operates in 27–31 GHz and contains 30 variables. Notably, The case is successfully synthesized without an initial solution and exhibits good in-band performance consistency. The obtained results demonstrate the potential of AI-driven PA design for future applications.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"498 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116546011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Synthesizable ADPLL Generator: From Specification to GDS","authors":"Kyumin Kwon, D. Wentzloff","doi":"10.1109/SMACD58065.2023.10192175","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192175","url":null,"abstract":"We propose an all-digital phase-locked loop (ADPLL) generator that automatically selects a design solution from a given input specifications and generates the layout using place-and-route (PnR) tool within 1.2 hours. While SPICE simulation-based modeling for a PLL is impractical due to its heavy computational intensity, all-digital architecture enables the use of theory-based frequency domain model for predicting the output specification, once the oscillator performance is characterized. The cell-based digitally controlled oscillator (DCO) is modeled by extracting the PDK and cell specific constants that characterizes the effective current to capacitance ratio from 3 sets of SPICE simulations. The constants are then used to predict the analog performance with an analytical model, which shows error rate less than 1.5% for estimating frequency range and power consumption. 8 generated PLL designs and their post-parasitic performances are compared to input specifications, including one measurement result from a fabricated chip in 65nm CMOS process.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121783414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Extraction of ECG features with spiking neurons for decreased power consumption in embedded devices","authors":"Zonglong Li, Laurie E. Calvet","doi":"10.1109/SMACD58065.2023.10192147","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192147","url":null,"abstract":"In recent years, the computational efficiency of spike-based biomimetic information processing has received increasing interest. Here we show by simulation how two spiking neurons with different thresholds can be used to extract ECG features. One high-threshold neuron detects the location of the heartbeat, and the other low-threshold neuron detects other small-magnitude features. These detected features alone can then be transmitted to a nearby computer to classify the heartbeat instead of the entire ECG signal. Reducing transferred data by about 50 times, minimizing energy consumption and thus potentially extending the continuous use time for health monitoring applications. We show that a KNN algorithm classifies the heartbeat based on the obtained features with an overall accuracy of 96%, proving our method’s feasibility.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127779351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Naya-Forcano, M. Garcia-Bosque, Guillermo Díez-Señorans, S. Celma
{"title":"Multiprogram tools for FPGA boards with single identifier on Windows","authors":"A. Naya-Forcano, M. Garcia-Bosque, Guillermo Díez-Señorans, S. Celma","doi":"10.1109/SMACD58065.2023.10192139","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192139","url":null,"abstract":"This paper explains the solution and tools developed to allow automated programming of multiple PYNQZ2 FPGA boards on the same Windows machine. This board uses the same internal identifier, so programming tools such as Vivado cannot differentiate between them and only reports one. Even though this is a particular problem, the use of different scripts and methods can help other researchers develop their own solutions.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122763576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Shunt-Shunt Feedback Inverter Transimpedance Amplifier Design for Capsule Endoscopy","authors":"Emrah Peker, O. Ferhanoğlu, M. B. Yelten","doi":"10.1109/SMACD58065.2023.10192154","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192154","url":null,"abstract":"This work reports on the design and performance of a shunt-shunt feedback inverter transimpedance amplifier (TIA). The proposed design is to be employed in capsule endoscopy with optical imaging or similar biomedical systems. The design is implemented in 180 nm CMOS technology with the performance targets of low area, low power, low complexity, high gain, and low noise. Alternative feedback resistor design approaches are proposed to achieve lower dispersion in transimpedance gain (TI gain), where one of the approaches proves superior in terms of area and performance. The design achieves 96 dBΩ gain with sub-0.6 dBΩ standard deviation in post-layout Monte Carlo simulations. The total input capacitance is 10 pF (from the photodiode), and the achieved −3 dB cut-off frequency is 50 MHz. The achieved total integrated input noise is 0.63 μA, and the total power consumption is 0.26 mW. Compared to similar works, the design improves power consumption and complexity without losing noise, and the TI gain performance considerably by keeping a narrow bandwidth, which is sufficient for the target operation.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128462410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Carlos Santos, Jorge R. Fernandes, Marcelino Santos, R. Martins
{"title":"Paving the Way for the Electronic Design Automation of Power Management Units","authors":"Carlos Santos, Jorge R. Fernandes, Marcelino Santos, R. Martins","doi":"10.1109/SMACD58065.2023.10192230","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192230","url":null,"abstract":"The inclusion of automation mechanisms in the intricate design of power management units (PMUs) is long pursued in industry. This paper carries a discussion on the research lines required to implement a tool that automatically produces, from the system-level until the ready-for-tape-out layout, complex PMUs when given a set of specifications. In that flow, at the IP level, simulation-based techniques are seen as a valuable solution to pursue optimal sizing and layout, and thus, for one of the charge pumps (CPs) required in the PMU, an academic tool is applied to determine the tradeoffs between performance and the, severely constrained, layout area. In the last step, a worst-case corner (WCC) optimization on a 45- and 99-dimensional design and performance spaces, respectively, derived from 9 time-consuming transient analysis of each candidate solution, provided a thorough analysis between worst-case efficiency, output resistance, and rise and fall times, impossible to perform in the manual design. The obtained insights on the design space will be used to speed-up the process of devising a solution for tape-out.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125245554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SMACD 2023 Cover Page","authors":"","doi":"10.1109/smacd58065.2023.10192215","DOIUrl":"https://doi.org/10.1109/smacd58065.2023.10192215","url":null,"abstract":"","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114582028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improving the Functional Coverage Closure of Network-on-Chip using Particle Swarm Optimization","authors":"N. Krishna, Aruna, J. Soumya","doi":"10.1109/SMACD58065.2023.10192207","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192207","url":null,"abstract":"Network-on-Chip (NoC) is a communication paradigm that has grown in favor as a solution for intra-chip communication in sophisticated System-on-Chip (SoC) architectures since it avoids complex interconnects. The functional verification of the NoC is a crucial phase in the design life-cycle of a NoC-based SoC because it has a direct impact on the SoC’s behavior and latency. Automating the NoC functional verification process could significantly reduce the time to market for such SoC designs. The employment of Particle Swarm Optimization to create NoC traffic which obtains maximal functional coverage in less simulation time is one such method of automation.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123913812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}