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2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)最新文献

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A detailed, cell-by-cell look into the effects of aging on an SRAM PUF using a specialized test array 使用专门的测试阵列对SRAM PUF老化的影响进行了详细的、逐细胞的研究
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2023-07-03 DOI: 10.1109/SMACD58065.2023.10192122
A. Santana-Andreo, P. Saraza-Canflanca, H. Carrasco-Lopez, R. Castro-López, E. Roca, F. Fernández
{"title":"A detailed, cell-by-cell look into the effects of aging on an SRAM PUF using a specialized test array","authors":"A. Santana-Andreo, P. Saraza-Canflanca, H. Carrasco-Lopez, R. Castro-López, E. Roca, F. Fernández","doi":"10.1109/SMACD58065.2023.10192122","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192122","url":null,"abstract":"The use of SRAM power-up values is the foundation of one of the most common Physical Unclonable Functions (PUFs) implementations, providing a Root-of-Trust for cryptographic applications at a low cost. PUFs are required to return the same response each time it is requested. However, SRAM power-ups by themselves are not reliable enough for the demanding PUF applications. This problem is solved by a variety of techniques that rely on an expected baseline reliability, extracted from tests performed under process, voltage and temperature variations. Nevertheless, aging effects, specifically Bias Temperature Instability (BTI), can have a significant impact that may not conform to the said baseline and are often ignored or overlooked due to the difficulty in properly characterizing and modeling them. In this work, we employ our custom chip specifically made to facilitate the characterization of aging through stress, i.e., applying a supply voltage larger than the nominal voltage to accelerate the impact of BTI and thus provide a more detailed look into the behavior of aging in an SRAM PUF array.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116417439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-Performance SET Hardening Technique for Vision-Oriented Applications 面向视觉应用的高性能SET硬化技术
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2023-07-03 DOI: 10.1109/SMACD58065.2023.10192201
C. D. Sio, L. Sterpone
{"title":"High-Performance SET Hardening Technique for Vision-Oriented Applications","authors":"C. D. Sio, L. Sterpone","doi":"10.1109/SMACD58065.2023.10192201","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192201","url":null,"abstract":"The decreasing feature size of VLSI circuits has led to a rise in Single Event Transients (SETs), making them the dominant cause of errors in modern VLSI devices, especially Flash-based FPGAs. The combinational logic in these devices is particularly vulnerable to SETs, making efficient SET hardening techniques essential. Given the demanding performance requirements for vision-oriented benchmarks, finding an efficient hardening technique that does not exceed area and performance limitations is challenging. This paper presents a SET hardening workflow based on an accurate SET analysis aimed at identifying vulnerable circuit nodes for selectively applying hardening techniques to Microchip RTG4 radiation-hardened Flash-based FPGAs. Results from experiments comparing plain, Global hardening, and proposed selective hardening techniques show the high efficiency of the proposed solution.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127739845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Overview of the Optimization of RF Power Amplifiers using a Bayesian Algorithm : (Invited) 基于贝叶斯算法的射频功率放大器优化研究综述(特邀)
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2023-07-03 DOI: 10.1109/SMACD58065.2023.10192208
Jialin Cai, Jia Guo, Yan Qu
{"title":"An Overview of the Optimization of RF Power Amplifiers using a Bayesian Algorithm : (Invited)","authors":"Jialin Cai, Jia Guo, Yan Qu","doi":"10.1109/SMACD58065.2023.10192208","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192208","url":null,"abstract":"An overview of the Bayesian approach to the optimization of broad-band radio frequency power amplifiers (PAs) is presented in this paper. Basic concepts associated with the Bayesian method, and existing Bayesian optimization (BO) methodologies for RF PAs with different acquisition functions (AFs) are described and compared. Additionally, the optimized PA results obtained using those optimization techniques are presented. Comparisons and discussions have been made between PAs using different Bayesian optimization algorithms.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133506833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Simplified Variability-Aware VCM Memristor Model for Efficient Circuit Simulation 一种用于高效电路仿真的简化可变感知VCM忆阻器模型
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2023-07-03 DOI: 10.1109/SMACD58065.2023.10192107
V. Ntinas, Dharmik Patel, Yongmin Wang, I. Messaris, V. Rana, S. Menzel, A. Ascoli, R. Tetzlaff
{"title":"A Simplified Variability-Aware VCM Memristor Model for Efficient Circuit Simulation","authors":"V. Ntinas, Dharmik Patel, Yongmin Wang, I. Messaris, V. Rana, S. Menzel, A. Ascoli, R. Tetzlaff","doi":"10.1109/SMACD58065.2023.10192107","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192107","url":null,"abstract":"Accurate and computationally cost-efficient models for fabricated memristor devices are essential for the design of future computers and AI-driven sensor-processor systems, especially for the simulation of large-scale circuits and systems. The variability-aware JART memristor model properly captures both the conduction mechanisms and the dynamical behavior of actual Valence Change Mechanism (VCM) memristors. However, the original JART VCM model incorporates an implicit description of the memristor current that constitutes a computationally heavy approach. Here, we aim to simplify the JART VCM model by replacing this implicit description with an explicit mathematical expression, leading to faster simulations and enabling deeper theoretical studies. The improvement achieved using the proposed model goes over x20 in simulation speed for increasing number of VCM devices, allowing for faster simulation of computing-inmemory and memristor-based AI systems.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114188494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of Low Power & Low Noise On-Chip BioAmplifier in Cooperation with Analog IC Synthesis at 130nm Skywater Technology 低功耗低噪声片上生物放大器的设计与模拟集成电路合成在130nm Skywater技术
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2023-07-03 DOI: 10.1109/SMACD58065.2023.10192202
Enes Saglican, Berkay Dur, Engin Afacan
{"title":"Design of Low Power & Low Noise On-Chip BioAmplifier in Cooperation with Analog IC Synthesis at 130nm Skywater Technology","authors":"Enes Saglican, Berkay Dur, Engin Afacan","doi":"10.1109/SMACD58065.2023.10192202","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192202","url":null,"abstract":"Biomedical applications require sensor interface circuits to process considerably low level signals in amplitude and predispose them for digital signal processing (DSP). One of the building blocks of a sensor interface is the bioamplifier, where the signals acquired from the body (EMG, ECG, ENG etc.) are first conditioned under certain constraints such as low noise, high gain, etc. Considering all these constraints and challenging trade-offs among them, design of the bioamplifier may become very complicated to be performed manually. In this paper, we present a low noise and low power bioamplifier, which has been designed with the aid of an analog circuit synthesis tool. To this end, all sub-blocks of the bioamplifier have been optimized via a multi-objective analog optimization tool, then these sub-blocks have been assembled to achieve the final design. All designs have been realized using 130nm Skywater technology parameters. Post-layout simulations have indicated that the design has an input referred noise of 12.8 μV rms, 0.017 mm2 chip area, and 7.25 μW power consumption. Also, Monte Carlo analysis has showed that the circuit can operate properly even under the process variations.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115183291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Peak Detect & Hold circuit to measure and exploit RTN in a 65-nm CMOS PUF 一个峰值检测和保持电路，用于测量和利用65nm CMOS PUF中的RTN
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2023-07-03 DOI: 10.1109/SMACD58065.2023.10192247
F. J. Rubio-Barbero, Eros Camacho-Ruiz, R. Castro-López, E. Roca, F. Fernández
{"title":"A Peak Detect & Hold circuit to measure and exploit RTN in a 65-nm CMOS PUF","authors":"F. J. Rubio-Barbero, Eros Camacho-Ruiz, R. Castro-López, E. Roca, F. Fernández","doi":"10.1109/SMACD58065.2023.10192247","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192247","url":null,"abstract":"A Physical Unclonable Function (PUF) that uses the Random Telegraph Noise (RTN) effect has been recently proposed. This PUF requires an analog sensing component whose design becomes critical to properly process the underlying entropy and thus provide a response to a given challenge. This analog sensing component needs to keep track of the RTN fluctuations through the detection and acquisition of the maximum and minimum excursions of a signal of interest that contains all the RTN information in a transistor. This paper describes the Peak Detect and Hold circuit that carries out that tracking, which has been designed with accuracy, reliability and fast dynamic response in mind. The proposed implementation has been designed in a 65-nm CMOS technology with a supply voltage of 1.2 V.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126732473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Layout Synthesis of Analog Primitive Cells with Variational Autoencoder 基于变分自编码器的模拟原始细胞布局合成
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2023-07-03 DOI: 10.1109/SMACD58065.2023.10192172
Po-Chun Wang, M. Lin, C. Liu, Hung-Ming Chen
{"title":"Layout Synthesis of Analog Primitive Cells with Variational Autoencoder","authors":"Po-Chun Wang, M. Lin, C. Liu, Hung-Ming Chen","doi":"10.1109/SMACD58065.2023.10192172","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192172","url":null,"abstract":"In analog layout design, the layout design styles of analog building blocks usually have the greatest impact on circuit performance. This paper introduces a new problem formulation and novel methodology for analog building block (a.k.a. primitive cell) layout synthesis. It extracts various building block placement and routing topologies from legacy layouts in the analog design repository, learns topologies through variational autoencoder, and finally synthesizes the building block layouts with the trained model as routing guidance. Experiment results show that the proposed approach can achieve even better performance compared with the conventional analog building block generation or migration approach.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124397493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modelling Memristive Devices via Ideal Memristor and Nonlinear Resistors 通过理想忆阻器和非线性电阻对忆阻器件进行建模
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2023-07-03 DOI: 10.1109/SMACD58065.2023.10192150
F. Corinto
{"title":"Modelling Memristive Devices via Ideal Memristor and Nonlinear Resistors","authors":"F. Corinto","doi":"10.1109/SMACD58065.2023.10192150","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192150","url":null,"abstract":"The paper shows that it is possible to exploit a combination of basic algebraic circuit elements corresponding to ideal memristors and nonlinear resistors in order to obtain the constitutive equation of a memristive device (a.k.a. extended memristor). By a suitable design of the characteristics of the constitutive elements, such extended memristors are able to approximate the model describing several real memristor devices.For the sake of simplicity, the work focuses on first–order memristor device described by the state–dependent Ohm’s law with a single internal variable, but the circuit design methodology proposed in this manuscript can be easily extended to develop memristor device models by identifying a linear resistive multiport connected to ideal memristors and nonlinear resistors.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129492016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electromigration Stress Analysis with Rational Krylov-based Approximation of Matrix Exponential 基于矩阵指数有理krylovv逼近的电迁移应力分析
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2023-07-03 DOI: 10.1109/SMACD58065.2023.10192185
Pavlos Stoikos, G. Floros, Dimitrios Garyfallou, N. Evmorfopoulos, G. Stamoulis
{"title":"Electromigration Stress Analysis with Rational Krylov-based Approximation of Matrix Exponential","authors":"Pavlos Stoikos, G. Floros, Dimitrios Garyfallou, N. Evmorfopoulos, G. Stamoulis","doi":"10.1109/SMACD58065.2023.10192185","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192185","url":null,"abstract":"With aggressive technology scaling, Electromigration (EM) has become a major concern for the semiconductor industry. Although analytical methods are typically used for accurate EM analysis of interconnects, they cannot be applied to general structures such as multi-segment trees. In this paper, we present a semi-analytical approach for transient EM analysis of interconnect trees, which enables the efficient calculation of EM-induced stress at any time and point independently. The proposed method exploits the rational Krylov subspace to accurately approximate the matrix exponential and accelerate the simulation of large EM models. Experimental evaluation on the OpenROAD benchmarks demonstrates that our method achieves 0.5% average relative error over the COMSOL industrial tool while being up to three orders of magnitude faster.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132535078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design considerations for a CMOS 65-nm RTN-based PUF CMOS 65nm rtn型PUF的设计考虑
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2023-07-03 DOI: 10.1109/SMACD58065.2023.10192200
Eros Camacho-Ruiz, F. J. Rubio-Barbero, R. Castro-López, E. Roca, F. Fernández
{"title":"Design considerations for a CMOS 65-nm RTN-based PUF","authors":"Eros Camacho-Ruiz, F. J. Rubio-Barbero, R. Castro-López, E. Roca, F. Fernández","doi":"10.1109/SMACD58065.2023.10192200","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192200","url":null,"abstract":"Physical Unclonable Functions (PUFs) have emerged as more secure alternatives to traditional Non-Volatile Memories in the field of hardware security. Recently, a novel PUF has been presented that uses the Random Telegraph Noise (RTN) phenomenon as the underlying source of entropy. To turn this concept into an integrated circuit, this paper provides a description of the transistor-level implementation of the PUF as well as a discussion on the constraints and requirements (both in functionality and testing capability) that a silicon implementation brings about. More specifically, the paper explores how to design and physically arrange the core elements of the RTN-PUF to efficiently use the silicon area and attain low PUF response times after a challenge is given.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114882110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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