Layout Synthesis of Analog Primitive Cells with Variational Autoencoder

Abstract

In analog layout design, the layout design styles of analog building blocks usually have the greatest impact on circuit performance. This paper introduces a new problem formulation and novel methodology for analog building block (a.k.a. primitive cell) layout synthesis. It extracts various building block placement and routing topologies from legacy layouts in the analog design repository, learns topologies through variational autoencoder, and finally synthesizes the building block layouts with the trained model as routing guidance. Experiment results show that the proposed approach can achieve even better performance compared with the conventional analog building block generation or migration approach.