Francesco Cosimi, J. Sini, Antonio Arena, M. Violante
{"title":"Novel Control Flow Checking Implementations for Automotive Software","authors":"Francesco Cosimi, J. Sini, Antonio Arena, M. Violante","doi":"10.1109/SMACD58065.2023.10192166","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192166","url":null,"abstract":"Safety-critical applications shall be implemented on highly dependable systems, and a part of their reliability is based on checking if the software is executed correctly. Various techniques are available for this purpose, like Control Flow Checking (CFC). Many CFC algorithms can be found in the literature, but their detection performances are assessed in theoretical scenarios, when implemented in Assembly language. The international standard on functional safety for automotive applications is ISO26262. It mandates to develop using high-level programming languages and the computation of the Diagnostic Coverage (DC). The DC measures the effectiveness of the chosen hardening method, in order to detect various Failure Modes (FMs). This paper discusses two alternative solutions, one software-only, and the other involving customized hardware, for these concerns: (i) address the FMs affecting the computation units described by Table 30 of part 11 of the ISO26262 (ii) guarantee the Freedom From Interference between the hardening method and the monitored entity.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130445927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Power Losses Analysis of SiC MOSFETs in DC-DC Converters with High-Ripple-Current Inductors","authors":"N. Femia, Hamidreza Jafarian, G. D. Capua","doi":"10.1109/SMACD58065.2023.10192180","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192180","url":null,"abstract":"This paper discusses behavioral models for power losses analysis of Silicon Carbide (SiC) MOSFETs in DC-DC converters, with emphasis on the impact of inductor saturation and peak-peak ripple current. All models are implemented in PathWave ADS software, by using symbolically defined devices. A PV-MPPT DC-DC boost converter is considered as a reference case study. The results confirm the advantages of working with large peak-peak ripple and partial saturation of power inductors.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115252033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hale Yilmaz, Kemal Ozanoglu, Pier Cavallini, M. Yazgi
{"title":"Single-Inductor Dual-Output DC-DC Converter with Multiple Flying Capacitors","authors":"Hale Yilmaz, Kemal Ozanoglu, Pier Cavallini, M. Yazgi","doi":"10.1109/SMACD58065.2023.10192121","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192121","url":null,"abstract":"This paper presents a novel single-inductor dual-output (SIDO) DC-DC converter topology with two flying capacitors. The two flying capacitors are located in the same current path, targeting an enhanced voltage drop reduction on the inductor, and a decrease in the inductor current slope, aiming for improved power efficiency and relaxed coil current constraints. Using specifications addressing battery-powered display driver applications, simulation results show up to 7.7% efficiency improvement compared to the conventional SIDO converter and up to 4.9% efficiency improvement compared to the SIDO converter with one flying capacitor topology. In addition, a reduction in inductor peak current and ripple can be achieved, along with a lower duty cycle operation, which all lead to relaxed coil selection criteria and relaxed converter stability constraints.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123762035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dominik Zupan, Daniel Kircher, N. Czepl, B. Deutschmann
{"title":"Framework to Simulate and Analyse the Electromagnetic Emission of Integrated Circuits under Electromagnetic Interference","authors":"Dominik Zupan, Daniel Kircher, N. Czepl, B. Deutschmann","doi":"10.1109/SMACD58065.2023.10192236","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192236","url":null,"abstract":"Ensuring the safe operation of electronic systems requires them to comply with electromagnetic compatibility (EMC) regulations. We can achieve this by conducting various EMC tests, including checking electromagnetic emission limits and immunity to interference signals, both on integrated circuit (IC) and on system level. However, these tests are typically performed separately, without considering the potential impact of one test on another. In this paper we present a framework to address this issue by simulation and subsequent post-processing. We focus on the impact of radio frequency (RF) disturbances on the electromagnetic emission of an IC, and propose a framework based on LTspice and Python, that implements the direct power injection (DPI) characterisation method and the 150 Ohm method. Within this paper we demonstrate the usability of this framework and how the resulting plot can support circuit designers in developing EMC compliant circuits. To do so, we utilise a test circuit, where the electromagnetic emission is significantly altered by an RF disturbance.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124931317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Long-Term Aging Impacts on Spatial On-Chip Power Density and Temperature","authors":"Sachin Sachdeva, Jinwei Zhang, H. Amrouch, S. Tan","doi":"10.1109/SMACD58065.2023.10192234","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192234","url":null,"abstract":"Long-term reliability, such as bias temperature instability (BTI) and hot-carrier injection (HCI), electromigration, etc., significantly impact the chip’s performance and lifetime. The existing approaches mainly focus on performance, such as delay and timing impacts, or only consider the BTI impacts on threshold voltage (VT ). However, the impact of BTI on power, specifically on the spatial power density and resulting thermal profile of a functional unit design, has not been thoroughly investigated. In this study, we evaluate the impact of BTI on both the spatial power density and temperature profiles of VLSI chips by considering its effects on multiple parameters of CMOS devices. Our findings show that BTI aging can lead to significant benefits in terms of on-chip temperature and the reduction of hot spots, especially at high operating temperatures, due to the decrease in power density. In this study, we focus on the impact of BTI aging on widely used circuits, such as dot product and dual-port synchronous RAM using a 45nm technology node. To account for the worst-case impact of BTI degradation, we utilized degradation-aware cell libraries that incorporate the maximum ΔVT of 63mV, i.e., is equivalent to 10 years of operation at Vdd=1.2V and T=130 °C. Our results indicate that after 10 years of operation, there is a significant impact on maximum power density for both the dot product and RAM circuits, with a reduction of around 5% and 7%, respectively. Similarly, there are noticeable maximum temperature changes, with a decrease of about 10% for the dot product and 6% for the RAM circuits.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125060446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modeling the Avalanche Breakdown of the FMMT417 NPN BJT in the TINA Environment","authors":"Mert Yetkin, M. B. Yelten","doi":"10.1109/SMACD58065.2023.10192129","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192129","url":null,"abstract":"In this paper, the avalanche breakdown observed in avalanche-type bipolar junction transistors is modeled, where a macromodel proposed earlier in the literature is extended to become compatible with practical circuit simulators. Moreover, contributions to the macromodel are introduced and implemented. The resulting model is used in circuit simulations, and the outcomes are compared with the experimental results that depict the accuracy of the proposed approach.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123253216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Fernández, E. Roca, P. Saraza-Canflanca, J. Martín-Martínez, R. Rodríguez, M. Nafría, R. Castro-López
{"title":"Strategies for parameter extraction of the time constant distribution of time-dependent variability models for nanometer-scale devices","authors":"F. Fernández, E. Roca, P. Saraza-Canflanca, J. Martín-Martínez, R. Rodríguez, M. Nafría, R. Castro-López","doi":"10.1109/SMACD58065.2023.10192206","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192206","url":null,"abstract":"Time-dependent variability phenomena are stochastic and discrete for nanometer-scale technologies, and, hence, must be statistically characterized. These phenomena are attributed to the emission and capture of charges in device defects. This paper explores two different strategies to extract, from experimental data, the distribution parameters of the time constants of the defects. It delves into the accuracy of each strategy, showing how the extraction strategy can have a huge impact on the accuracy and the amount of characterization data required, and, therefore, on the amount of (expensive) characterization time in the lab.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123879778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Francesco Borgioli, Roberto Pio Baorda, Paolo Angelini
{"title":"Time based architecture for high-side current sensor with integrated shunt resistor","authors":"Francesco Borgioli, Roberto Pio Baorda, Paolo Angelini","doi":"10.1109/SMACD58065.2023.10192119","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192119","url":null,"abstract":"This paper presents a fully integrated current sensor based on an integrated shunt resistor supporting a 25V common mode input while operating at 1.2V supply voltage. It can detect a current between ±4A. It uses a novel time based architecture to increase sensor accuracy over temperature, mechanical stress and lifetime. This architecture is based on the integration of a replica of the current to sense using a switched capacitor integrator with reset working with a very accurate clock signal. With this technique sensor’s gain is not sensitive to temperature variation, mechanical stress or lifetime variation of the shunt resistor. On the other hands, its accuracy is limited only by a capacitor and the clock period variation. Their variation are much smaller than the ones of a resistor. The overall gain of this architecture achieves a precision of 1/1000 over temperature variation.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125279126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Exploitation of Subharmonic Injection Locking for Solving Combinatorial Optimization Problems with Coupled Oscillators using VO2 based devices","authors":"J. Núñez, M. Avedillo, M. Jiménèz","doi":"10.1109/SMACD58065.2023.10192227","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192227","url":null,"abstract":"Coupled nano-oscillators are attracting increasing interest because of their potential to perform computation efficiently, enabling new applications in computing and information processing. The potential of phase transition devices for such dynamical systems has recently been recognized. This paper investigates the implementation of coupled VO2 based oscillators networks for solving Max-Cut combinatorial optimization problems. The Max-Cut model is mapped to an Ising model which is solved by the synchronization dynamics of the system. The impact of subharmonic injection locking on the probability of the system to reach the ground state of the Ising Hamiltonian and so the optimum solution to the corresponding optimization problem is analyzed.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131283611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jose M. Gata-Romero, A. Santana-Andreo, E. Roca, R. Castro-López, F. Fernández
{"title":"A Test Module for Aging Characterization of Digital Circuits","authors":"Jose M. Gata-Romero, A. Santana-Andreo, E. Roca, R. Castro-López, F. Fernández","doi":"10.1109/SMACD58065.2023.10192112","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192112","url":null,"abstract":"In digital circuits, aging phenomena can lead to timing violations due to increased signal delays suffered by digital cells. An accurate and trustworthy characterization of these mechanisms in modern nanometer CMOS technologies is essential, for which accelerated aging tests are the typical experimental procedure used. This type of test makes it possible to observe aging degradation without waiting for years of circuit operation, by raising voltage and temperature conditions above their nominal values. These stress conditions have a major impact on how the cell under test will be affected by aging degradation. This paper presents a new highly versatile test module whose purpose is to generate AC and DC signals with different amplitudes and, in the case of AC signals, also with different frequencies, to stress a digital cell in a wide variety of scenarios.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129923915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}