Modeling the Avalanche Breakdown of the FMMT417 NPN BJT in the TINA Environment

Abstract

In this paper, the avalanche breakdown observed in avalanche-type bipolar junction transistors is modeled, where a macromodel proposed earlier in the literature is extended to become compatible with practical circuit simulators. Moreover, contributions to the macromodel are introduced and implemented. The resulting model is used in circuit simulations, and the outcomes are compared with the experimental results that depict the accuracy of the proposed approach.