NVSystolic: Heterogeneous Simulation Framework for Emerging Memories with Systolic Array

In recent years, hardware accelerators have shown significant advantages in the field of deep neural networks. The architecture used in such systems has high memory utilization. To make the most of memory technology in conjunction with compute fabric, careful study of memory optimisation is thus necessary. NVSystolic, a heterogeneous simulation framework based on reconfigurable memory subsystems with a systolic array serving as the computing unit, is presented in this study. In particular, Non-Volatile Memory (NVM) can be modelled by the framework for the systolic array-based accelerator.