NVSystolic: Heterogeneous Simulation Framework for Emerging Memories with Systolic Array

Chithambara Moorthii, Sufyan Khan, M. Suri
{"title":"NVSystolic: Heterogeneous Simulation Framework for Emerging Memories with Systolic Array","authors":"Chithambara Moorthii, Sufyan Khan, M. Suri","doi":"10.1109/SMACD58065.2023.10192216","DOIUrl":null,"url":null,"abstract":"In recent years, hardware accelerators have shown significant advantages in the field of deep neural networks. The architecture used in such systems has high memory utilization. To make the most of memory technology in conjunction with compute fabric, careful study of memory optimisation is thus necessary. NVSystolic, a heterogeneous simulation framework based on reconfigurable memory subsystems with a systolic array serving as the computing unit, is presented in this study. In particular, Non-Volatile Memory (NVM) can be modelled by the framework for the systolic array-based accelerator.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"34 2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMACD58065.2023.10192216","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

In recent years, hardware accelerators have shown significant advantages in the field of deep neural networks. The architecture used in such systems has high memory utilization. To make the most of memory technology in conjunction with compute fabric, careful study of memory optimisation is thus necessary. NVSystolic, a heterogeneous simulation framework based on reconfigurable memory subsystems with a systolic array serving as the computing unit, is presented in this study. In particular, Non-Volatile Memory (NVM) can be modelled by the framework for the systolic array-based accelerator.
NVSystolic:基于收缩阵列的新兴记忆异构仿真框架
近年来,硬件加速器在深度神经网络领域显示出显著的优势。在这种系统中使用的架构具有很高的内存利用率。为了充分利用内存技术与计算结构的结合,仔细研究内存优化是必要的。提出了一种以收缩阵列为计算单元,基于可重构存储子系统的异构仿真框架NVSystolic。特别是,非易失性存储器(NVM)可以通过收缩阵列加速器的框架来建模。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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