Design Flow to Develop Wideband Inverter-Based Circuits Using C/ID Methodology

Abstract

A systematic design flow based on C/ID methodology for developing high-speed inverter-based amplifiers will be proposed, with the goal to minimize design iterations and maintain high precision. This methodology enables designers to select the most energy- and power-efficient amplifier topology based on target requirements, especially operating speed. For this study, an established CMOS 28 nm technology is utilized, wherein, the performance of inverter-based amplifiers is compared against the conventional continuous-time differential amplifier topologies, i.e., differential PFET and NFET Current-Mode Logic (CML) circuits. The proposed design methodology shows less than ± 5% mismatch to the transistor-level simulations.