Shut Off! – Hybrid BICMOS Logic for Power-Efficient High Speed Circuits

Abstract

Power efficiency is crucial, especially in high-speed systems, where conventional approaches like clock gating cannot be employed readily. Special logic families, such as Positive Emitter-Coupled Logic (PECL), push the technological frontier, promising even more speed at the expense of an even more strained power budget. We propose a novel hybrid of PECL and Complementary Metal-Oxide-Semiconductor (CMOS) logic to introduce Function Shut-off (FSO), realizing a shut-off at the level of functional blocks and logic primitives inside complex logic cells. Using this approach, we realize a high-speed Linear Feedback Shift Register (LFSR) in a SiGe technology, extending the State of the Art (SOTA) by adding reconfigurability, which is required for its use as sequence generator in Compressed Sensing (CS) applications. We present measurements showing successful fabrication and performance of the packaged die at 20.4 GHz. In this LFSR, employing FSO reduces the supply current by a factor of up to four (depending on the chosen configuration) and reduces active area by 17%.