{"title":"用C/ID方法开发宽带逆变电路的设计流程","authors":"Behdad Jamadi, Fariborz T. Ordubadi, A. Tajalli","doi":"10.1109/SMACD58065.2023.10192184","DOIUrl":null,"url":null,"abstract":"A systematic design flow based on C/ID methodology for developing high-speed inverter-based amplifiers will be proposed, with the goal to minimize design iterations and maintain high precision. This methodology enables designers to select the most energy- and power-efficient amplifier topology based on target requirements, especially operating speed. For this study, an established CMOS 28 nm technology is utilized, wherein, the performance of inverter-based amplifiers is compared against the conventional continuous-time differential amplifier topologies, i.e., differential PFET and NFET Current-Mode Logic (CML) circuits. The proposed design methodology shows less than ± 5% mismatch to the transistor-level simulations.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design Flow to Develop Wideband Inverter-Based Circuits Using C/ID Methodology\",\"authors\":\"Behdad Jamadi, Fariborz T. Ordubadi, A. Tajalli\",\"doi\":\"10.1109/SMACD58065.2023.10192184\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A systematic design flow based on C/ID methodology for developing high-speed inverter-based amplifiers will be proposed, with the goal to minimize design iterations and maintain high precision. This methodology enables designers to select the most energy- and power-efficient amplifier topology based on target requirements, especially operating speed. For this study, an established CMOS 28 nm technology is utilized, wherein, the performance of inverter-based amplifiers is compared against the conventional continuous-time differential amplifier topologies, i.e., differential PFET and NFET Current-Mode Logic (CML) circuits. The proposed design methodology shows less than ± 5% mismatch to the transistor-level simulations.\",\"PeriodicalId\":239306,\"journal\":{\"name\":\"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-07-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMACD58065.2023.10192184\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMACD58065.2023.10192184","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design Flow to Develop Wideband Inverter-Based Circuits Using C/ID Methodology
A systematic design flow based on C/ID methodology for developing high-speed inverter-based amplifiers will be proposed, with the goal to minimize design iterations and maintain high precision. This methodology enables designers to select the most energy- and power-efficient amplifier topology based on target requirements, especially operating speed. For this study, an established CMOS 28 nm technology is utilized, wherein, the performance of inverter-based amplifiers is compared against the conventional continuous-time differential amplifier topologies, i.e., differential PFET and NFET Current-Mode Logic (CML) circuits. The proposed design methodology shows less than ± 5% mismatch to the transistor-level simulations.