{"title":"Stitch-Aware Routing Considering Smart Boundary for Multiple E-Beam Lithography","authors":"Chih-Hsiang Hsu, Shao-Yun Fang","doi":"10.1109/VLSI-DAT49148.2020.9196298","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196298","url":null,"abstract":"As one of competitive next generation lithography (NGL), multiple electron beam lithography (MEBL) has been proposed to improve the low throughput issue. For this maskless lithography, each field is split into stripes that are slightly overlapped with each other, and each stripe of layout patterns is written by a single electron beam (e-beam). If a pattern lies on an overlapped region (stitching region) of two neighboring stripes, it can be written by either of the two e-beams, which is known as smart boundary. To avoid layout features written by more than one e-beam and thus suffering from the overlay error between different beams, we propose a full-chip router utilizing smart boundary to minimize stitch-sensitive patterns. Experimental results show that the proposed algorithm can produce stitch-friendly routing solutions and thus greatly improve MEBL manufacturability and yield.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128174390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Millimeter-Wave Frequency Synthesizer for 60 GHz Wireless Interconnect","authors":"Yong-Yu Lin, Fan-ta Chen, Wei-Zen Chen","doi":"10.1109/VLSI-DAT49148.2020.9196262","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196262","url":null,"abstract":"A millimeter-wave (mmW) frequency synthesizer for 60GHz wireless transceiver is presented. To achieve wide range and low noise operation, a new sampling PD based PLL (S-PLL) is proposed. In contrast to conventional sub-sampling PD based PLLs, it provides a wider capture range without suffering from harmonic lock problems. Also, compared to conventional CP-based PLLs, the inband noise is improved by 13 dB while the reference spur is improved by more than 16 dB. Implemented in TSMC 28nm CMOS technology, the core circuit occupies a chip area of 0.175mm2. The measured phase noise from a 48 GHz carrier is -95.7dBc/Hz at 1MHz offset. The power consumption is 54mW.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133711139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automatic Floorplanning for AI SoCs","authors":"Tai-Chen Chen, Pei-Yu Lee, Tung-Chieh Chen","doi":"10.1109/VLSI-DAT49148.2020.9196464","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196464","url":null,"abstract":"In recent years, artificial intelligence/deep learning field is growing rapidly. The AI system-on-chip designs are actively developed. These designs often have properties of many IP blocks/embedded memories and complicated logic interconnect. In this paper, we propose an automatic floorplanning algorithm by using dataflow information and design exploration techniques to obtain high quality mixed macro and cell placement to handle numerous macros and complicated logic interconnect in AI SoCs.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127741108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An SIMO Step-Down Converter with Coupled Inductor","authors":"Yi-Chieh Hsu, Jing-Yuan Lin, Chii-Hwa Wang, Sz-Wei Chou","doi":"10.1109/VLSI-DAT49148.2020.9196435","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196435","url":null,"abstract":"Power management IC have been widely used, and due to the development of the process, the number of transistors on the same area has grown, resulting in more sets of output requirements. The single-inductor multi-output power converter not only meets the requirements of multiple sets of voltages today, but also greatly reduces the area and cost of the system. This thesis uses a single-coupled inductor to achieve multiple output. The chip is implemented in TSMC 0.35 $mu$m2P4M CMOS process, and the internal control circuit and power transistor and PADs have a die area of 1. 69975$times$ 3.78275mm2. The input voltage range is 4.5$sim $5.5 V and the first output voltage is 1.2 V, the second output voltage is 1.8 V, and the external power stage coupled inductor and capacitor are 2 $mu$H and 330 $mu$F respectively.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127892473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Experiments and optimizations for TVM on RISC-V Architectures with P Extension","authors":"Yi-Ru Chen, Hui-Hsin Liao, Chia-Hsuan Chang, Che-Chia Lin, Chao-Lin Lee, Yuan-Ming Chang, Chun-Chieh Yang, Jenq-Kuen Lee","doi":"10.1109/VLSI-DAT49148.2020.9196477","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196477","url":null,"abstract":"TVM is a AI compiler supports both graph-level and operator-level optimization on machine learning models. It provides an optimizable flow to deploy on diverse target devices. By exploiting TVM schedule, we can optimize the codegen behavior for our RISC-V architecture. Since RISCV is configurable with the selection on different extension, we can enable multiple extensions depends on the application scene. In our work, we present the flow for enabling and optimizing the RISC-V P extension toward QNN models from TVM. With support from LLVM and a customized deep learning runtime (DLR), we verified our work on both FLOAT32 and prequantized models from Tensorflow Lite. Experiments shows that comparing with FLOAT32 models, our work can achieve 2.7-7.0 times of performance improvement with regard to total instruction count at runtime for pre-quantized version with a set of benchmarks including Mobilenet and Inception-v3. As for accuracy issue, the degradation is tiny for quantization version among 500 images. All experiments are running on RISC-V simulator, Spike with P extension support.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129950724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design Solutions for 5G Power Amplifiers using 0.15μm and 0.25μm GaN HEMTs","authors":"Yi-Qi Lin, A. Patterson","doi":"10.1109/VLSI-DAT49148.2020.9196306","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196306","url":null,"abstract":"This paper presents Power Amplifier solutions for 5G using GaN SiC HEMT technology. The difference in performance between $0.15 mu mathrm{m}$ and $0.25 mu mathrm{m}$ GaN HEMT devices is discussed. Measurements show $0.25 mu mathrm{m}$ GaN HEMTs provide good performance for applications up to 18 GHz, including excellent performance in the Sub-6 GHz 5G bands. $0.15 mu mathrm{m}$ GaN HEMTs currently offer good performance for applications to more than 32 GHz, including excellent performance in the 24-28 GHz 5G mm-wave band. Variations on the $0.15 mu mathrm{m}$ process are also being developed to extend the operation frequency to cover the US 5G mm-wave band at 39 GHz and operation over 40 GHz to include Q band Satellite. This paper discusses performance of a discrete GaN power transistor (power bar) DC - 14GHz, with high power density and PAE in a single stage transistor that offers strong performance suitable for Sub-6 GHz 5G. It also discusses performance of a 2-stage 5W PA MMIC 24-28 GHz which is ideally suited for mm-wave 5G.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130775795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Integrated Group-based Valuable Sensor Selection Approach for Remaining Machinery Life Estimation in the Future Industry 4.0 Era","authors":"K. Chen, Zi-Jie Gao","doi":"10.1109/VLSI-DAT49148.2020.9196260","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196260","url":null,"abstract":"Industry 4.0 is the evolution trend for current manufacturing technology. By analyzing the real-time sensing data, the health status of each machinery is usually monitored to reduce the risk of suddenly machine failure. Although massive sensors allocation can leverage the Remaining Useful Life (RUL) estimation for each machinery, the cost for the sensor network construction will become expensive. Hence, it is necessary to have an approach to remove the redundant sensors under a certain constraint of RUL estimation. On the other hand, due to the attractive performance on the object classification, many researches apply Artificial Neural Network (ANN) to decide which allocated sensor should be removed during the training process. However, the current researches aim to remove the redundant sensors based on the sensing data at a specific time, which lacks the intrinsic feature of time-series sensing data. Therefore, the current researches suffer from the problem of sensor under-killing due to the worst-case consideration. In this paper, we consider the information of time-series sensing data to propose an integrated group-based valuable sensor selection algorithm. Because the proposed approach considers the historical data during the redundant sensor removing process, we can reduce the number of involved allocated sensors precisely and significantly. In order to verify the proposed method, we use the Commercial Modular Aero-Propulsion System Simulation (CMAPSS) dataset and adopt Prognostics and Health Management (PHM) score to evaluate the RUL estimation performance. Compared with the conventional approach, the proposed approach can reduce 86% average PHM score and employ fewer sensors to fit the strict constraint of PHM score with less computing overhead.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130974802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis and Design of a Self-Charged Crystal Oscillator with Pulse Regulating Feedback Loop","authors":"Hsiang-Chun Cheng, Yu-Hong Yang, Tai-Cheng Lee","doi":"10.1109/VLSI-DAT49148.2020.9196439","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196439","url":null,"abstract":"A 32.768-kHz self-charged crystal oscillator (SCXO) using a proposed pulse regulator is presented. The general equation for pulse injection also provides a different insight for evaluating energy injected in crystal (XTAL). A robust oscillation with low power consumption is possible for a 1-V power supply. The proposed pulsed-regulated SCXO is designed in a 40-nm CMOS technology and the simulation shows 65.6% power reduction with process corner variation. In addition, the analytical locked amplitude of the proposed circuit is simulated and verified.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130976625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Cost-Effective Embedded Nonvolatile Memory with Scalable LEE Flash®-G2 SONOS for Secure IoT and Computing-in-Memory (CiM) Applications","authors":"K. Nii, Y. Taniguchi, K. Okuyama","doi":"10.1109/VLSI-DAT49148.2020.9196270","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196270","url":null,"abstract":"We introduce a cost-effective, reliable and energy efficient embedded flash memory technology and its applications. A charge trapping type of Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) with twin select-gates structure has been demonstrated on 55-nm bulk CMOS technology. It is potentially scalable on advanced fully depleted (FD)-SOI or 3D Fin-FET devices below 28-nm node. Those feasibilities are shown by TCAD simulations and existing 55-nm planar bulk silicon data. Secure and low-power applications are introduced that are using nonvolatile (NV)-SRAM by combining with SRAM cell and flash cell. Besides, analog computing-inmemory (CiM) based on flash is also introduced for energy efficient artificial intelligence (AI) applications in edge computing.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"310 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131935455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"5G mmWAVE Technology Design Challenges and Development Trends","authors":"Wen-Chiang Chen","doi":"10.1109/VLSI-DAT49148.2020.9196316","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196316","url":null,"abstract":"The explosive growth in areas of mobile subscriber, wireless network access, mobile services and applications shows evidences of the continuous expansion of cellular communication bandwidth requirement. The 5G (fifth generation) mobile communication standard aims to solve the substantially increased requirement of data rate and the avalanche of traffic volume. One of the promising solutions is to use the millimeter wave frequency band to get the wide available spectrum. To overcome these unfavorable channel properties, i.e. high path loss, propagation loss, rain fading…,e.t.c., the beam-forming, beam tracking together with phased array antenna are the most crucial key technologies.In this paper, we describe the system specifications and the design considerations of the architecture for the RF and beam forming of the 5G mmWave communication system. Then the design challenges and development trends of the 5G mmWave front-end module are presented. Finally, ITRI’s developed 28GHz 5G millimeter-wave development and verification platform is introduced which adopts the hybrid beam-forming architecture designed with a 8/16/32/64-antenna phased antenna array for gNB and/or UE to implement the beam-forming technology, also a beam-tracking algorithm is developed to support the mobile transmission over 100Km/hr.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132278576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}