{"title":"AI soc的自动地板规划","authors":"Tai-Chen Chen, Pei-Yu Lee, Tung-Chieh Chen","doi":"10.1109/VLSI-DAT49148.2020.9196464","DOIUrl":null,"url":null,"abstract":"In recent years, artificial intelligence/deep learning field is growing rapidly. The AI system-on-chip designs are actively developed. These designs often have properties of many IP blocks/embedded memories and complicated logic interconnect. In this paper, we propose an automatic floorplanning algorithm by using dataflow information and design exploration techniques to obtain high quality mixed macro and cell placement to handle numerous macros and complicated logic interconnect in AI SoCs.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Automatic Floorplanning for AI SoCs\",\"authors\":\"Tai-Chen Chen, Pei-Yu Lee, Tung-Chieh Chen\",\"doi\":\"10.1109/VLSI-DAT49148.2020.9196464\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In recent years, artificial intelligence/deep learning field is growing rapidly. The AI system-on-chip designs are actively developed. These designs often have properties of many IP blocks/embedded memories and complicated logic interconnect. In this paper, we propose an automatic floorplanning algorithm by using dataflow information and design exploration techniques to obtain high quality mixed macro and cell placement to handle numerous macros and complicated logic interconnect in AI SoCs.\",\"PeriodicalId\":235460,\"journal\":{\"name\":\"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-DAT49148.2020.9196464\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196464","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In recent years, artificial intelligence/deep learning field is growing rapidly. The AI system-on-chip designs are actively developed. These designs often have properties of many IP blocks/embedded memories and complicated logic interconnect. In this paper, we propose an automatic floorplanning algorithm by using dataflow information and design exploration techniques to obtain high quality mixed macro and cell placement to handle numerous macros and complicated logic interconnect in AI SoCs.
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