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2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)最新文献

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A 500nW-50μ W Indoor Photovoltaic Energy Harvester with Multi-mode MPPT 一种500nW-50μ W多模MPPT室内光伏能量采集器
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196387
Ming-Chia Chang, Min-Hsuan Wu, Shen-Iuan Liu
{"title":"A 500nW-50μ W Indoor Photovoltaic Energy Harvester with Multi-mode MPPT","authors":"Ming-Chia Chang, Min-Hsuan Wu, Shen-Iuan Liu","doi":"10.1109/VLSI-DAT49148.2020.9196387","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196387","url":null,"abstract":"A 500nW$- 50 mu mathrm{W}$ indoor photovoltaic energy harvester is presented with a multi-mode maximum power point tracking (MPPT) circuit. Three switched-capacitor DC-DC converters (SCDCs) with different switch sizes and flying capacitors are realized. A multi-mode MPPT circuit is presented to tune the voltage conversion ratios and the switching frequency of the SCDCs. In addition, this multi-mode MPPT circuit also utilizes three reconfigurable SCDCs to cover the input power range of 500nW $sim 50 mu mathrm{W}$. This indoor photovoltaic energy harvester is realized in a 0.18m CMOS process and its active area is 1.15mm2. The measured peak power conversion efficiency is 64.4%.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121507875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Intelligent Architectures for Intelligent Machines 智能机器的智能架构
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196490
O. Mutlu
{"title":"Intelligent Architectures for Intelligent Machines","authors":"O. Mutlu","doi":"10.1109/VLSI-DAT49148.2020.9196490","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196490","url":null,"abstract":"Computing is bottlenecked by data. Large amounts of application data overwhelm storage capability, communication capability, and computation capability of the modern machines we design today. As a result, many key applications’ performance, efficiency and scalability are bottlenecked by data movement. In this keynote talk, we describe three major shortcomings of modern architectures in terms of 1) dealing with data, 2) taking advantage of the vast amounts of data, and 3) exploiting different semantic properties of application data. We argue that an intelligent architecture should be designed to handle data well. We show that handling data well requires designing architectures based on three key principles: 1) data-centric, 2) data-driven, 3) data-aware. We give several examples for how to exploit each of these principles to design a much more efficient and high performance computing system. We especially discuss recent research that aims to fundamentally reduce memory latency and energy, and practically enable computation close to data, with at least two promising novel directions: 1) performing massively-parallel bulk operations in memory by exploiting the analog operational properties of memory, with low-cost changes, 2) exploiting the logic layer in 3D-stacked memory technology in various ways to accelerate important data-intensive applications. We discuss how to enable adoption of such fundamentally more intelligent architectures, which we believe are key to efficiency, performance, and sustainability. We conclude with some guiding principles for future computing architecture and system designs.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126480154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A Noise-shaping SAR Assisted MASH 2-1 Sigma-Delta Modulator 噪声整形SAR辅助math2 -1 σ - δ调制器
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196468
Yu-Sian Lin, Soon-Jyh Chang, Chia-Ling Wei
{"title":"A Noise-shaping SAR Assisted MASH 2-1 Sigma-Delta Modulator","authors":"Yu-Sian Lin, Soon-Jyh Chang, Chia-Ling Wei","doi":"10.1109/VLSI-DAT49148.2020.9196468","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196468","url":null,"abstract":"This paper presents a noise-shaping SAR assisted MASH 2-1 sigma-delta modulator (SDM). To implement a SDM with high resolution and high speed, the resolution of the quantizer and the noise-shaping order must rise with a low oversampling ratio (OSR). Based on the proposed MASH structure, the noise-shaping order can be raised, and also the number of OPAMPs and the mismatch effect among different stages can be reduced. Furthermore, two quantizers in the proposed MASH structure are combined into a noise-shaping quantizer for easy implementation. The proof-of-concept prototype was fabricated in TSMC 90-nm CMOS technology. At 1.0V supply, sampling rate of 80-MS/s, bandwidth of 3.333 MHz, the prototype achieves 71.44 dB SNDR. Besides, the slope of it verifies the almost 3rd noise-shaping successfully.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133047573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 5.4GHz ΔΣ Bang-Bang PLL with 19dB In-Band Noise Reduction by Using a Nested PLL Filter 一种5.4GHz ΔΣ Bang-Bang锁相环，采用嵌套锁相环滤波器，带内噪声降低19dB
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196454
Xiaohua Huang, Bowen Wang, W. Rhee, Zhihua Wang
{"title":"A 5.4GHz ΔΣ Bang-Bang PLL with 19dB In-Band Noise Reduction by Using a Nested PLL Filter","authors":"Xiaohua Huang, Bowen Wang, W. Rhee, Zhihua Wang","doi":"10.1109/VLSI-DAT49148.2020.9196454","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196454","url":null,"abstract":"This paper presents an in-band noise reduction method for $Delta Sigma$ fractional-N bang-bang phase locked loops (BBPLLs) by using a nested integer-N BBPLL in the feedback path that works as a phase-domain low-pass filter (PDLPF). A prototype 5.4GHz $Delta Sigma$ fractional-N BBPLL is implemented in 65nm CMOS. The proposed $Delta Sigma$ fractional-N BBPLL achieves the in-band noise reduction of 19dB when the PDLPF is enabled. Experimental results show that the PDLPF method is useful for the $Delta Sigma$ fractional-N BBPLL not only to suppress the out-of-band noise but also to mitigate the in-band noise degradation.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133792827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Resistor-Based Temperature Sensing Chip with Digital Output 基于电阻的数字输出温度传感芯片
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196448
Kai-Min Chang, Yen-Ju Lin, Chia-Liang Wei, Soon-Jyh Chang
{"title":"Resistor-Based Temperature Sensing Chip with Digital Output","authors":"Kai-Min Chang, Yen-Ju Lin, Chia-Liang Wei, Soon-Jyh Chang","doi":"10.1109/VLSI-DAT49148.2020.9196448","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196448","url":null,"abstract":"In this work, a smart temperature sensing chip is proposed for the applications of internet-of-things and wearable devices. A resistor-based temperature sensing bridge is integrated with a fully differential difference amplifier, a 10-bit successive approximation analog-to-digital converter, and timing circuits into a single chip. This chip is designed to sense temperature once per second, and is activated only 64 $mu$ S per second and stays in the standby mode in the rest of time for reducing power consumption. The proposed chip is designed and fabricated by a 0.18m 1P6M mixed-signal process, and the total area is $953 times 708$ $mu m^{2}$. According to the measured results, the linearity between the measured temperature and the digital output is excellent, and it can work with a supply voltage ranging from 1.4 V to 2.0V.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117166173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A CMOS Temperature Sensor Based on a Chopped Continuous-Time Delta-Sigma Modulator 基于斩波连续时间δ - σ调制器的CMOS温度传感器
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196368
Po-Yu Li, Wei-En Lee, Ching-Tzung Lin, Li-Te Wu, Tsung-Hsien Lin
{"title":"A CMOS Temperature Sensor Based on a Chopped Continuous-Time Delta-Sigma Modulator","authors":"Po-Yu Li, Wei-En Lee, Ching-Tzung Lin, Li-Te Wu, Tsung-Hsien Lin","doi":"10.1109/VLSI-DAT49148.2020.9196368","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196368","url":null,"abstract":"A resistor-based temperature sensor with a 2nd-order 1-bit continuous-time delta-sigma modulator (CTDSM) to realize an energy-efficient temperature sensor is presented. The chopping technique is applied to alleviate the offset and flicker noise of the 1st-stage amplifier. A finite impulse response (FIR) filter is incorporated in the feedback path to mitigate noise fold-back due to chopping operation. The proposed circuit, implemented in 0.18-μm CMOS, consumes 183.6 μW from a 1.8-V supply. With a single conversion time of 333.3 μs, the temperature resolution is less than 3.71 m°C (1δ), which leads to a Figure of merit (FoM) of 0.84 pJ°C2. The 3δ temperature inaccuracy of 8 chips under a range of −40 °C to 100 °C is 3.8 °C after 1-point and batch calibration.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129819853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 12-bit 100-kS/s SAR ADC for IoT Applications 用于物联网应用的12位100 k /s SAR ADC
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196440
Yung-Hui Chung, Qi-Feng Zeng
{"title":"A 12-bit 100-kS/s SAR ADC for IoT Applications","authors":"Yung-Hui Chung, Qi-Feng Zeng","doi":"10.1109/VLSI-DAT49148.2020.9196440","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196440","url":null,"abstract":"This paper presents a low-power 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC) for IoT applications. The SAR ADC uses an adaptive sampler to increase the input tracking time and reduce the probability of metastability. A cyclic loop delay control circuit is proposed to optimize the total conversion time for this 12-bit SAR ADC. Furthermore, the capacitor swapping scheme is applied to maintain better ADC linearity with a smaller total capacitance and relax the ADC input driving capability. The prototype ADC was fabricated in a 180-nm CMOS technology. It consumes a total power of $1.15 mu mathrm{W}$ from a 0.7-V supply at 100-kS/s. With the capacitor swapping scheme, the measured SNDR and SFDR are 63.7 and 84 dB, respectively. With the MSB weight correction, the measured ENOB is 10.8 bits, equivalent to a peak figure-of-merit of 6.6 fJ/conversion-step.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126933796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hardware Architecture and Implementation of Clustered Tensor Approximation for Multi-Dimensional Visual Data 多维视觉数据聚类张量逼近的硬件结构与实现
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196449
C. Yang, Yang-Ming Yeh, Yi-Chang Lu
{"title":"Hardware Architecture and Implementation of Clustered Tensor Approximation for Multi-Dimensional Visual Data","authors":"C. Yang, Yang-Ming Yeh, Yi-Chang Lu","doi":"10.1109/VLSI-DAT49148.2020.9196449","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196449","url":null,"abstract":"Tensor approximation has been proven to be an efficient and flexible dimensionality reduction method. However, for applications which require rapid image rendering, the computational cost of data reconstruction after applying tensor approximation is still high. As a result, several modified tensor approximation algorithms supporting fast reconstruction have been proposed, where clustered tensor approximation (CTA) is one of those which are often mentioned. In this paper, we design a hardware accelerator for CTA. The processor can handle a tensor of size $12mathrm{S}times 12mathrm{S}times 12mathrm{S}times 12mathrm{S}$. With parallel processing techniques, the performance of the processor can achieve a $ 9.41times $ speed-up when compared to the software.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123315859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Real-time Error Monitoring System Considering Endurance and Data-retention Characteristics of TaOX-based ReRAM Storage with Workloads at Data Centers 考虑数据中心工作负载下基于taox的ReRAM存储持久性和数据保留特性的实时错误监控系统
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196379
Yoshiki Kakuta, Reika Kinoshita, H. Kinoshita, C. Matsui, K. Takeuchi
{"title":"Real-time Error Monitoring System Considering Endurance and Data-retention Characteristics of TaOX-based ReRAM Storage with Workloads at Data Centers","authors":"Yoshiki Kakuta, Reika Kinoshita, H. Kinoshita, C. Matsui, K. Takeuchi","doi":"10.1109/VLSI-DAT49148.2020.9196379","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196379","url":null,"abstract":"Approximate Computing attracts attention due to reducing power consumption and improving performance by tolerating errors. However, to use Approximate Computing, systems should control amounts of errors occurred in storage. This paper proposes real-time error monitoring system using ReRAM storage in order to understand how many errors occur in storage. To evaluate this system, measured ReRAM data and one-week long workload logs at data centers are input to the proposed system. The proposed system outputs Total bit error rate (BER) calculated from Set/Reset cycles and write interval time. In addition, the proposed system reveals that Total BER of some sectors exceeds the error correction limit set to 0.9 code rate of BCH ECC for a week.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133546530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CORONA: A k-COnnected RObust Interconnection Network Generation Algorithm CORONA:一种k连接鲁棒互联网络生成算法
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196220
Hsin-I Wu, R. Tsay, Fong-Yuan Chang
{"title":"CORONA: A k-COnnected RObust Interconnection Network Generation Algorithm","authors":"Hsin-I Wu, R. Tsay, Fong-Yuan Chang","doi":"10.1109/VLSI-DAT49148.2020.9196220","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196220","url":null,"abstract":"In the paper, we propose a k-connected robust interconnection network (k-RN) for open fault tolerance and design a k-RN generation algorithm to handle large interconnected networks. In a k-RN, any vertex pair has at least k disjoint connections and can tolerate k-l opens. To realize k RN in current large networks, we design an effective $O(nlog n)$-time algorithm, Corona, with a novel approach for total connection length reduction. Experiments in IC design application show that Corona can practically handle large nets with 100k pins in a few minutes each. The quality in terms of total wire length of Corona is within 1.6% on average to an $O(n^{3})$-time approximation algorithm, and within 4.7% to exact optimum solutions.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131009509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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