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2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)最新文献

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Low-Active-Energy and Low-Standby-Power Sub-threshold ROM for IoT Edge Sensing Systems 面向物联网边缘传感系统的低有功功耗和低待机功耗亚阈值ROM
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196482
Jinn-Shyan Wang, Chien-Tung Liu, Chao-Hsiang Wang
{"title":"Low-Active-Energy and Low-Standby-Power Sub-threshold ROM for IoT Edge Sensing Systems","authors":"Jinn-Shyan Wang, Chien-Tung Liu, Chao-Hsiang Wang","doi":"10.1109/VLSI-DAT49148.2020.9196482","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196482","url":null,"abstract":"Key design goals of the sub-threshold ROM for IoT sensing systems are reducing active energy and standby power. A conventional ROM used NAND bit-lines with a source-line scheme to conquer noise issues and a code-inversion scheme to improve performance. This work adopts OAI bit-lines to increase the Ion/Ioff ratio for lowering the Vmin. It reduces energy and power consumption by removing source drivers and code-inversion circuitry. The proposed 256-Kb 90nm OAI-ROM operates at 0.22V and achieves 62% and 70% reduction in active energy and standby power, respectively, compared to the NAND-ROM.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127619036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS 标准CMOS微卫星抗辐射RISC处理器
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196348
H. Chiueh, Chia-Hsiang Yang, Charles H.-P. Wen, Chao-Guang Yang, Po-Hao Chien, Ching-Yang Hung, Yu-Jui Chen, Yao-Pin Wang, Chin-Fong Chiu, Jer Lin
{"title":"Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS","authors":"H. Chiueh, Chia-Hsiang Yang, Charles H.-P. Wen, Chao-Guang Yang, Po-Hao Chien, Ching-Yang Hung, Yu-Jui Chen, Yao-Pin Wang, Chin-Fong Chiu, Jer Lin","doi":"10.1109/VLSI-DAT49148.2020.9196348","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196348","url":null,"abstract":"An integrated design framework is proposed to automate radiation-harden (rad-hard) VLSI systems in a standard CMOS technology. TMR, DICE, SERL, ELT, and ECC techniques are integrated across architecture, circuit, and layout levels. Performance of the rad-hard cells were evaluated in 0.18m CMOS. A rad-hard RISC processor targeting for an inclination micro-satellite on a 720km orbit was realized in 90nm CMOS. The chip was tested by applying heavy ions with corresponding radiation dose. The rad-hard RISC processor functions under all the test conditions (LET $ lt 101.5$ MeV-cm $^{2} /$ mg), validating the effectiveness of the methodology.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114292129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a High-Throughput and Area-Efficient Ultra-Long FFT Processor 一种高吞吐量和面积高效的超长FFT处理器的设计
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196280
H. Lin, Pin-Han Lin, Chih-Wei Liu
{"title":"Design of a High-Throughput and Area-Efficient Ultra-Long FFT Processor","authors":"H. Lin, Pin-Han Lin, Chih-Wei Liu","doi":"10.1109/VLSI-DAT49148.2020.9196280","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196280","url":null,"abstract":"In recent years, many popular technologies require a highthroughput ultra-long FFT processor, such as the OFDM and FMCW radars. In order to get high throughput, we use the MDC architecture to design the FFT processor. In addition, we added the 2-epoch architecture [1] to reduce the area of FIFOs in the MDC processor. Since the input to the MDC FFT is not in natural order, we need to design a reorder circuit. We proposed a data-scheduling algorithm that allows the reorder circuit to use the least number of memory banks to achieve area reduction. Furthermore, we proposed a twiddle-factorgenerator circuit for the 2-epoch architecture. It can effectively reduce the number of twiddle factors that need to be stored. We designed different specifications of FFT processors using the method described in this paper, and then synthesized using the TSMC 90 nm CMOS technology high-Vt standard cell library. Our processors can operate above 450MHz and the throughput is $Pcdot R$, where P is the parallelism of hardware and the R is the operating frequency.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121128862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fault-Aware ECC Techniques for Reliability Enhancement of Flash Memory 提高闪存可靠性的故障感知ECC技术
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196286
Shyue-Kung Lu, Zeng-Long Tsai, Chun-Lung Hsu, Chi-Tien Sun
{"title":"Fault-Aware ECC Techniques for Reliability Enhancement of Flash Memory","authors":"Shyue-Kung Lu, Zeng-Long Tsai, Chun-Lung Hsu, Chi-Tien Sun","doi":"10.1109/VLSI-DAT49148.2020.9196286","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196286","url":null,"abstract":"Due to the rapid process scaling trend and reduced cell size, flash memory faces more and more challenges in reliability and endurance. This dilemma becomes more critical in multilevel flash memory due to the tight spacing between adjacent programmed levels. Error correction codes with stronger protection capability are usually adopted to all flash pages as a solution. However, the growth of raw bit error rate (RBER) induced by increasing P/E cycles will lead to uneven distribution of errors. Applying uniform ECC protection capability for all flash pages might incur unnecessary hardware overhead and latency. In this paper, fault-aware error correction code (PECC) techniques are proposed to cure these drawbacks of uniform protection. The main idea is to upgrade the ECC protection levels for flash pages when their correction slack is below the specified threshold. An ECC SRAM and an ECC CAM are used for storing extra check bits and accessing purposes. According to experimental results, we can enhance the reliability of flash memories with negligible hardware cost.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"253 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121883759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
RFIC and RF Module for 5G Applications 5G应用的RFIC和RF模块
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196407
Ming-Da Tsai, Song-Yu Yang, Chi-Yao Yu, Ping-Yu Chen, Tzung-Han Wu, Mohammed Hassan, Chi-Tsan Chen, Chao-Wei Wang, Yen-Chuan Huang, Li-Han Huang, W. Chiu, A. Lin, Bo-Yu Lin, Arnaud Werquin, Chien-Cheng Lin, Yen-Horng Chen, Jen-Che Tsai, Yuan-Yu Fu, B. Tenbroek, Chinq-Shiun Chiu, Yi-Bin Lee, G. Dehng
{"title":"RFIC and RF Module for 5G Applications","authors":"Ming-Da Tsai, Song-Yu Yang, Chi-Yao Yu, Ping-Yu Chen, Tzung-Han Wu, Mohammed Hassan, Chi-Tsan Chen, Chao-Wei Wang, Yen-Chuan Huang, Li-Han Huang, W. Chiu, A. Lin, Bo-Yu Lin, Arnaud Werquin, Chien-Cheng Lin, Yen-Horng Chen, Jen-Che Tsai, Yuan-Yu Fu, B. Tenbroek, Chinq-Shiun Chiu, Yi-Bin Lee, G. Dehng","doi":"10.1109/VLSI-DAT49148.2020.9196407","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196407","url":null,"abstract":"In this work, a 12nm CMOS 2/3/4/5G multi-RAT (Radio Access Technology) XCVR is presented, capable of supporting up to 6 inter-band CA DL with flexible 4x4 MIMO port selection and 2 inter-band CA UL with coherent 2x2 MIMO. In NR 200MHz 4x4 MIMO 256QAM mode a throughput up to 5Gbps can be achieved. This work is housed in 2-layer Flip-Chip Chip-Scale Package (FCCSP).","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117205640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1-200MHz Multiple Output Fractional Divider Using Phase Rotating Technique 采用相位旋转技术的1-200MHz多输出分数分压器
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196213
Chun-Yu Lin, T. Wang, Yu-Ting Hung, Tsung-Hsien Lin
{"title":"A 1-200MHz Multiple Output Fractional Divider Using Phase Rotating Technique","authors":"Chun-Yu Lin, T. Wang, Yu-Ting Hung, Tsung-Hsien Lin","doi":"10.1109/VLSI-DAT49148.2020.9196213","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196213","url":null,"abstract":"An open-loop fractional output divider (FOD) using phase rotating technique is presented. A phase rotating technique is adopted to reduce the dynamic range of digitalto-time converter (DTC) for output jitter improvement. This prototype is implemented in a 90-nm CMOS process. It can operate over a frequency range of 0.635 MHz to 162.5 MHz. At 160-MHz output frequency, it consumes 6.29 mW from 1-V supply. The measured phase noises at 1-MHz offset is 135.8 dBc/Hz and it achieves 1.19 psrms integrated jitter (10 kHz to 30 MHz).","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132140569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel Minimum Variance Beamformer and Its Circuit Design for Ultrasound Beamforming 一种新型超声波束形成最小方差波束形成器及其电路设计
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196432
Ming Khuan Son, Neng-Jian Sim, T. Chiueh
{"title":"A Novel Minimum Variance Beamformer and Its Circuit Design for Ultrasound Beamforming","authors":"Ming Khuan Son, Neng-Jian Sim, T. Chiueh","doi":"10.1109/VLSI-DAT49148.2020.9196432","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196432","url":null,"abstract":"This paper describes new approaches to minimum variance distortionless response (MVDR) beamforming for coherent plane-wave compounding (CPWC) in ultrasound imaging. Imaging results based on actual received and simulated waveforms show improvements over the traditional Delay and Sum (DAS) method as well as other MVDR-based methods, in terms of spatial and contrast resolutions. We designed detail circuits that can be configured to implement several of the aforementioned ultrasound beamforming methods effectively. The simulated operating frequency for the circuits implemented in FPGA is up to 62. 5MHz.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123582476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Video Dehazing Hardware Accelerator Design based on Dark Channel Prior with Sky Preservation 基于暗通道先验和天空保存的视频去雾硬件加速器设计
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196353
Zi-Yi Zhao, An-Tia Xiao, Jiun-In Guo
{"title":"Video Dehazing Hardware Accelerator Design based on Dark Channel Prior with Sky Preservation","authors":"Zi-Yi Zhao, An-Tia Xiao, Jiun-In Guo","doi":"10.1109/VLSI-DAT49148.2020.9196353","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196353","url":null,"abstract":"With the increasingly serious haze disaster, the development of dehazing technology is highly concerned. But the current software dehazing algorithm suffers from too high computational complexity. We selects the algorithm based on dark channel prior with sky preservation [1] as the base software algorithm, and a hardware accelerator is designed to simplify the data transmission process and optimize the data processing. The whole operation simulation of the accelerator is realized in NC-Verilog hardware design environment. The accelerator can achieve 75fps@640x480 video dehazing under 0.18$mu$m CMOS technology. It can be applied to driving assistance and surveillance system.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114259379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Flexible Multi-Precision Accelerator Design for Deep Convolutional Neural Networks Considering Both Data Computation and Communication 考虑数据计算和通信的深度卷积神经网络柔性多精度加速器设计
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196465
Shen-Fu Hsiao, Yu-Hong Chen
{"title":"Flexible Multi-Precision Accelerator Design for Deep Convolutional Neural Networks Considering Both Data Computation and Communication","authors":"Shen-Fu Hsiao, Yu-Hong Chen","doi":"10.1109/VLSI-DAT49148.2020.9196465","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196465","url":null,"abstract":"Due to the quick advance in deep convolutional neural networks (CNN), hardware acceleration of convolution computations for edge devices is crucial for many artificial intelligence applications. This paper presents a CNN accelerator design that supports various CNN filter sizes/strides and different bit precisions. In particular, we analyze the latency of data communication and computation and determine the proper precision that maximizes the utilization efficiency of available hardware resource. The proposed design supports data precision of 8-bit and 16-bit, and weight precision of 2-bit, 4-bit, 8-bit, and 16-bit for popular CNN models. It can effectively increase speed performance of low-precision computation by exploiting the additional parallelism.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125021205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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