Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS

Abstract

An integrated design framework is proposed to automate radiation-harden (rad-hard) VLSI systems in a standard CMOS technology. TMR, DICE, SERL, ELT, and ECC techniques are integrated across architecture, circuit, and layout levels. Performance of the rad-hard cells were evaluated in 0.18m CMOS. A rad-hard RISC processor targeting for an inclination micro-satellite on a 720km orbit was realized in 90nm CMOS. The chip was tested by applying heavy ions with corresponding radiation dose. The rad-hard RISC processor functions under all the test conditions (LET $ \lt 101.5$ MeV-cm $^{2} /$ mg), validating the effectiveness of the methodology.