A 1-200MHz Multiple Output Fractional Divider Using Phase Rotating Technique

Abstract

An open-loop fractional output divider (FOD) using phase rotating technique is presented. A phase rotating technique is adopted to reduce the dynamic range of digitalto-time converter (DTC) for output jitter improvement. This prototype is implemented in a 90-nm CMOS process. It can operate over a frequency range of 0.635 MHz to 162.5 MHz. At 160-MHz output frequency, it consumes 6.29 mW from 1-V supply. The measured phase noises at 1-MHz offset is 135.8 dBc/Hz and it achieves 1.19 psrms integrated jitter (10 kHz to 30 MHz).