2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)最新文献_第3页

An Imu-Based Wearable Ring For On-Surface Handwriting Recognition 一种基于imu的可穿戴式手写识别环

2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196479

Zhe-Ting Liu, Davy P. Y. Wong, Pai H. Chou

引用次数: 3

MiniDeviation: An Efficient Multi-Stage Bus-Aware Global Router MiniDeviation:一种高效的多级总线感知全局路由器

2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196219

Weida Zhu, Xinghai Zhang, Genggeng Liu, Wenzhong Guo, Ting-Chi Wang

引用次数: 3

Reliability Analysis of Reconfiguration Controller for FPGA–Based Fault Tolerant Systems: Case Study 基于fpga的容错系统重构控制器可靠性分析

2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196269

R. Panek, Jakub Lojda, Jakub Podivinsky, Z. Kotásek

{"title":"Reliability Analysis of Reconfiguration Controller for FPGA–Based Fault Tolerant Systems: Case Study","authors":"R. Panek, Jakub Lojda, Jakub Podivinsky, Z. Kotásek","doi":"10.1109/VLSI-DAT49148.2020.9196269","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196269","url":null,"abstract":"This paper deals with a reliability analysis of a reconfiguration controller which can be a component of a faulttolerant control system. This controller is designed for an FPGA to be capable of using partial dynamic reconfiguration of the FPGA to mitigate potential faults in the FPGA’s configuration memory. These faults, which are called SEUs, can be induced by radiation effects. Therefore, fault tolerance measurement or estimation is very important for designing circuits for critical environments. Thus, the reliability of the reconfiguration controller itself is significant; therefore the Fault Tolerance ESTimation (FT-EST) framework is used for reliability evaluation, which is procured by the discovery of a number of critical configuration bits. Two approaches are used and compared: evaluations of used LUT only, and evaluations of all configuration bits. We ascertained a 20x reduction in time consumption at the expense of a proportional decrease in the amount of critical configuration bits discovered. The obtained results are nearly equivalent.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122933802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A 0.5-V, 1.79-μW, 250-kbps Wake-up Receiver for IoT application in 90-nm CMOS 一种用于物联网应用的0.5 v, 1.79 μ w, 250kbps的90纳米CMOS唤醒接收器

2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196261

Zhen-Cheng Zhang, Chun-Yuan Chiu, Hsiang-Cheng Yuan, Tsung-Hsien Lin

引用次数: 1

A 24 Mbit/s Red LED-based Visible Light Communication System Employing DCO-OFDM Modulation 采用DCO-OFDM调制的24mbit /s红色led可见光通信系统

2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196282

Yu-Jung Wang, Siou-Lin You, Zhen-Hao Zhu, Wei-Ting Lin, Cheng-You Ho, Chi-Lun Hsu, Chun-Hsing Lee, Hsi-Pin Ma

引用次数: 0

Miniaturized CMOS imaging device for implantable applications 用于植入式应用的小型化CMOS成像器件

2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196250

K. Sasagawa, M. Haruta, Yasumi Ohta, H. Takehara, J. Ohta

引用次数: 0

Deep Learning Creativity in EDA EDA中的深度学习创造力

2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196288

C. Lee

引用次数: 2

Fault-Tolerance Mechanism Analysis on NVDLA-Based Design Using Open Neural Network Compiler and Quantization Calibrator 基于开放神经网络编译器和量化校准器的nvdla容错机制分析

2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196335

Shu-Ming Liu, Luba Tang, N. Huang, Der-Yu Tsai, Ming Yang, Kai-Chiang Wu

{"title":"Fault-Tolerance Mechanism Analysis on NVDLA-Based Design Using Open Neural Network Compiler and Quantization Calibrator","authors":"Shu-Ming Liu, Luba Tang, N. Huang, Der-Yu Tsai, Ming Yang, Kai-Chiang Wu","doi":"10.1109/VLSI-DAT49148.2020.9196335","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196335","url":null,"abstract":"The NVIDIA Deep Learning Accelerator (NVDLA) provides free intellectual property licensing to IC chip vendors and researchers to build a chip that uses deep neural networks for inference applications. The Open Neural Network Compiler (ONNC) provides an extensible compiler, a quantization calibrator and optimization supports for running DNN models on NVDLA-based SoCs. Even with open-sourced NVDLA and ONNC, conducting the development of an AI chip still brings up many productivity issues in the mass production stage, such as SRAM MBIST (Memory Built-In Self Test) fail, scan-chain fail etc. When applying Fault-Tolerance Mechanism in error-tolerant applications such as image classification by using the AI CNN model, this paper presents a light-weight Fault-Tolerance Mechanism to effectively enhance the robustness of NVDLA-based edge AI chip when encountering internal SRAM stuck fault. Our non-accurate MAC calculation for the whole convolution computation leads to a very promising quality of results compared to the case when an exactly accurate convolution operation is used. The Fault-Tolerance Mechanism analysis and design described in this paper can also apply to the similar fixed-point deep learning accelerator design, and opens new opportunities for research as well as product development.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123778708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Low-Power 3D-PCB Stacking System Design and Validation by Automatic Voltage-Current Scalable Technique 基于电压电流自动扩展技术的低功耗3D-PCB堆叠系统设计与验证

2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196244

Ching-Hwa Cheng, Jiun-In Guo

引用次数: 0

Cost-Effective Reliable Edge Computing Hardware Design Based on Module Simplification and Duplication: A Case Study on Vehicle Detection Based on Support Vector Machine 基于模块简化和复制的高性价比可靠边缘计算硬件设计——以支持向量机车辆检测为例

2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI: 10.1109/VLSI-DAT49148.2020.9196386

Tong-Yu Hsieh, Hsin-Yung Shen, Chia-Teng Hsu

{"title":"Cost-Effective Reliable Edge Computing Hardware Design Based on Module Simplification and Duplication: A Case Study on Vehicle Detection Based on Support Vector Machine","authors":"Tong-Yu Hsieh, Hsin-Yung Shen, Chia-Teng Hsu","doi":"10.1109/VLSI-DAT49148.2020.9196386","DOIUrl":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196386","url":null,"abstract":"Autonomous vehicles and advanced driver assistance systems (ADAS) have recently become quite popular research topics. While autonomous vehicles may not be totally ready now, ADAS has been applied to many vehicles. The implementation of ADAS partly relies on detection of vehicles via edge computing. However, the edge computing hardware may age and incur functional errors. Soft errors may also be caused due to cosmic charged particles. These errors may invalidate the vehicle detection result, thereby incurring serious safety threats. In this paper we investigate on designing a cost-effective reliable edge computing circuit. A case study on vehicle detection is considered where a support vector machine is implemented for illustration purpose. We find that in edge computing hardware, several multiplier-accumulator (MAC) units can be removed without sacrificing detection accuracy. A simple yet effective procedure is also proposed to identify such MAC units. The saved hardware can then be utilized to protect the remaining hardware, reducing the required hardware cost. Numeric fault simulations are first performed to identify which circuit lines need to be protected such that there is no loss on the vehicle detection accuracy due to faults. Then, for these lines, proper protection methods are investigated based on evaluation of their required hardware cost and fault-induced accuracy loss. Accordingly a hybrid protection scheme is developed, which achieves up to 153% hardware cost reduction when compared to the typical TMR-based protection method.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127221741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0