一种新型超声波束形成最小方差波束形成器及其电路设计

Ming Khuan Son, Neng-Jian Sim, T. Chiueh
{"title":"一种新型超声波束形成最小方差波束形成器及其电路设计","authors":"Ming Khuan Son, Neng-Jian Sim, T. Chiueh","doi":"10.1109/VLSI-DAT49148.2020.9196432","DOIUrl":null,"url":null,"abstract":"This paper describes new approaches to minimum variance distortionless response (MVDR) beamforming for coherent plane-wave compounding (CPWC) in ultrasound imaging. Imaging results based on actual received and simulated waveforms show improvements over the traditional Delay and Sum (DAS) method as well as other MVDR-based methods, in terms of spatial and contrast resolutions. We designed detail circuits that can be configured to implement several of the aforementioned ultrasound beamforming methods effectively. The simulated operating frequency for the circuits implemented in FPGA is up to 62. 5MHz.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A Novel Minimum Variance Beamformer and Its Circuit Design for Ultrasound Beamforming\",\"authors\":\"Ming Khuan Son, Neng-Jian Sim, T. Chiueh\",\"doi\":\"10.1109/VLSI-DAT49148.2020.9196432\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes new approaches to minimum variance distortionless response (MVDR) beamforming for coherent plane-wave compounding (CPWC) in ultrasound imaging. Imaging results based on actual received and simulated waveforms show improvements over the traditional Delay and Sum (DAS) method as well as other MVDR-based methods, in terms of spatial and contrast resolutions. We designed detail circuits that can be configured to implement several of the aforementioned ultrasound beamforming methods effectively. The simulated operating frequency for the circuits implemented in FPGA is up to 62. 5MHz.\",\"PeriodicalId\":235460,\"journal\":{\"name\":\"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-DAT49148.2020.9196432\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196432","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

介绍了超声成像中相干平面波复合(CPWC)的最小方差无失真响应波束形成的新方法。基于实际接收和模拟波形的成像结果表明,在空间和对比度分辨率方面,与传统的延迟和求和(DAS)方法以及其他基于mvdr的方法相比,该方法得到了改进。我们设计了详细的电路,可以配置以有效地实现上述几种超声波束形成方法。在FPGA上实现的电路的模拟工作频率高达62。5 mhz。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Novel Minimum Variance Beamformer and Its Circuit Design for Ultrasound Beamforming
This paper describes new approaches to minimum variance distortionless response (MVDR) beamforming for coherent plane-wave compounding (CPWC) in ultrasound imaging. Imaging results based on actual received and simulated waveforms show improvements over the traditional Delay and Sum (DAS) method as well as other MVDR-based methods, in terms of spatial and contrast resolutions. We designed detail circuits that can be configured to implement several of the aforementioned ultrasound beamforming methods effectively. The simulated operating frequency for the circuits implemented in FPGA is up to 62. 5MHz.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信