标准CMOS微卫星抗辐射RISC处理器

2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI:10.1109/VLSI-DAT49148.2020.9196348

H. Chiueh, Chia-Hsiang Yang, Charles H.-P. Wen, Chao-Guang Yang, Po-Hao Chien, Ching-Yang Hung, Yu-Jui Chen, Yao-Pin Wang, Chin-Fong Chiu, Jer Lin

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引用次数: 0

摘要

提出了一种集成设计框架，在标准的CMOS技术中实现自动化抗辐射(rad-hard) VLSI系统。TMR, DICE, SERL, ELT和ECC技术集成在架构，电路和布局级别上。在0.18m CMOS中评估了抗辐射电池的性能。在90nm CMOS上实现了针对720km轨道倾斜微卫星的雷达硬RISC处理器。用相应辐射剂量的重离子对芯片进行了测试。radhard RISC处理器在所有测试条件下运行(LET $ \lt 101.5$ MeV-cm $^{2} /$ mg)，验证了该方法的有效性。

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Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS

An integrated design framework is proposed to automate radiation-harden (rad-hard) VLSI systems in a standard CMOS technology. TMR, DICE, SERL, ELT, and ECC techniques are integrated across architecture, circuit, and layout levels. Performance of the rad-hard cells were evaluated in 0.18m CMOS. A rad-hard RISC processor targeting for an inclination micro-satellite on a 720km orbit was realized in 90nm CMOS. The chip was tested by applying heavy ions with corresponding radiation dose. The rad-hard RISC processor functions under all the test conditions (LET $ \lt 101.5$ MeV-cm $^{2} /$ mg), validating the effectiveness of the methodology.

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2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

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