A 12-bit 100-kS/s SAR ADC for IoT Applications

Abstract

This paper presents a low-power 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC) for IoT applications. The SAR ADC uses an adaptive sampler to increase the input tracking time and reduce the probability of metastability. A cyclic loop delay control circuit is proposed to optimize the total conversion time for this 12-bit SAR ADC. Furthermore, the capacitor swapping scheme is applied to maintain better ADC linearity with a smaller total capacitance and relax the ADC input driving capability. The prototype ADC was fabricated in a 180-nm CMOS technology. It consumes a total power of $1.15 \mu \mathrm{W}$ from a 0.7-V supply at 100-kS/s. With the capacitor swapping scheme, the measured SNDR and SFDR are 63.7 and 84 dB, respectively. With the MSB weight correction, the measured ENOB is 10.8 bits, equivalent to a peak figure-of-merit of 6.6 fJ/conversion-step.