Yoshiki Kakuta, Reika Kinoshita, H. Kinoshita, C. Matsui, K. Takeuchi
{"title":"考虑数据中心工作负载下基于taox的ReRAM存储持久性和数据保留特性的实时错误监控系统","authors":"Yoshiki Kakuta, Reika Kinoshita, H. Kinoshita, C. Matsui, K. Takeuchi","doi":"10.1109/VLSI-DAT49148.2020.9196379","DOIUrl":null,"url":null,"abstract":"Approximate Computing attracts attention due to reducing power consumption and improving performance by tolerating errors. However, to use Approximate Computing, systems should control amounts of errors occurred in storage. This paper proposes real-time error monitoring system using ReRAM storage in order to understand how many errors occur in storage. To evaluate this system, measured ReRAM data and one-week long workload logs at data centers are input to the proposed system. The proposed system outputs Total bit error rate (BER) calculated from Set/Reset cycles and write interval time. In addition, the proposed system reveals that Total BER of some sectors exceeds the error correction limit set to 0.9 code rate of BCH ECC for a week.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Real-time Error Monitoring System Considering Endurance and Data-retention Characteristics of TaOX-based ReRAM Storage with Workloads at Data Centers\",\"authors\":\"Yoshiki Kakuta, Reika Kinoshita, H. Kinoshita, C. Matsui, K. Takeuchi\",\"doi\":\"10.1109/VLSI-DAT49148.2020.9196379\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Approximate Computing attracts attention due to reducing power consumption and improving performance by tolerating errors. However, to use Approximate Computing, systems should control amounts of errors occurred in storage. This paper proposes real-time error monitoring system using ReRAM storage in order to understand how many errors occur in storage. To evaluate this system, measured ReRAM data and one-week long workload logs at data centers are input to the proposed system. The proposed system outputs Total bit error rate (BER) calculated from Set/Reset cycles and write interval time. In addition, the proposed system reveals that Total BER of some sectors exceeds the error correction limit set to 0.9 code rate of BCH ECC for a week.\",\"PeriodicalId\":235460,\"journal\":{\"name\":\"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"volume\":\"123 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-DAT49148.2020.9196379\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196379","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Real-time Error Monitoring System Considering Endurance and Data-retention Characteristics of TaOX-based ReRAM Storage with Workloads at Data Centers
Approximate Computing attracts attention due to reducing power consumption and improving performance by tolerating errors. However, to use Approximate Computing, systems should control amounts of errors occurred in storage. This paper proposes real-time error monitoring system using ReRAM storage in order to understand how many errors occur in storage. To evaluate this system, measured ReRAM data and one-week long workload logs at data centers are input to the proposed system. The proposed system outputs Total bit error rate (BER) calculated from Set/Reset cycles and write interval time. In addition, the proposed system reveals that Total BER of some sectors exceeds the error correction limit set to 0.9 code rate of BCH ECC for a week.