{"title":"一种5.4GHz ΔΣ Bang-Bang锁相环,采用嵌套锁相环滤波器,带内噪声降低19dB","authors":"Xiaohua Huang, Bowen Wang, W. Rhee, Zhihua Wang","doi":"10.1109/VLSI-DAT49148.2020.9196454","DOIUrl":null,"url":null,"abstract":"This paper presents an in-band noise reduction method for $\\Delta \\Sigma$ fractional-N bang-bang phase locked loops (BBPLLs) by using a nested integer-N BBPLL in the feedback path that works as a phase-domain low-pass filter (PDLPF). A prototype 5.4GHz $\\Delta \\Sigma$ fractional-N BBPLL is implemented in 65nm CMOS. The proposed $\\Delta \\Sigma$ fractional-N BBPLL achieves the in-band noise reduction of 19dB when the PDLPF is enabled. Experimental results show that the PDLPF method is useful for the $\\Delta \\Sigma$ fractional-N BBPLL not only to suppress the out-of-band noise but also to mitigate the in-band noise degradation.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 5.4GHz ΔΣ Bang-Bang PLL with 19dB In-Band Noise Reduction by Using a Nested PLL Filter\",\"authors\":\"Xiaohua Huang, Bowen Wang, W. Rhee, Zhihua Wang\",\"doi\":\"10.1109/VLSI-DAT49148.2020.9196454\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an in-band noise reduction method for $\\\\Delta \\\\Sigma$ fractional-N bang-bang phase locked loops (BBPLLs) by using a nested integer-N BBPLL in the feedback path that works as a phase-domain low-pass filter (PDLPF). A prototype 5.4GHz $\\\\Delta \\\\Sigma$ fractional-N BBPLL is implemented in 65nm CMOS. The proposed $\\\\Delta \\\\Sigma$ fractional-N BBPLL achieves the in-band noise reduction of 19dB when the PDLPF is enabled. Experimental results show that the PDLPF method is useful for the $\\\\Delta \\\\Sigma$ fractional-N BBPLL not only to suppress the out-of-band noise but also to mitigate the in-band noise degradation.\",\"PeriodicalId\":235460,\"journal\":{\"name\":\"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-DAT49148.2020.9196454\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196454","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 5.4GHz ΔΣ Bang-Bang PLL with 19dB In-Band Noise Reduction by Using a Nested PLL Filter
This paper presents an in-band noise reduction method for $\Delta \Sigma$ fractional-N bang-bang phase locked loops (BBPLLs) by using a nested integer-N BBPLL in the feedback path that works as a phase-domain low-pass filter (PDLPF). A prototype 5.4GHz $\Delta \Sigma$ fractional-N BBPLL is implemented in 65nm CMOS. The proposed $\Delta \Sigma$ fractional-N BBPLL achieves the in-band noise reduction of 19dB when the PDLPF is enabled. Experimental results show that the PDLPF method is useful for the $\Delta \Sigma$ fractional-N BBPLL not only to suppress the out-of-band noise but also to mitigate the in-band noise degradation.