{"title":"考虑智能边界的多电子束光刻缝线感知路由","authors":"Chih-Hsiang Hsu, Shao-Yun Fang","doi":"10.1109/VLSI-DAT49148.2020.9196298","DOIUrl":null,"url":null,"abstract":"As one of competitive next generation lithography (NGL), multiple electron beam lithography (MEBL) has been proposed to improve the low throughput issue. For this maskless lithography, each field is split into stripes that are slightly overlapped with each other, and each stripe of layout patterns is written by a single electron beam (e-beam). If a pattern lies on an overlapped region (stitching region) of two neighboring stripes, it can be written by either of the two e-beams, which is known as smart boundary. To avoid layout features written by more than one e-beam and thus suffering from the overlay error between different beams, we propose a full-chip router utilizing smart boundary to minimize stitch-sensitive patterns. Experimental results show that the proposed algorithm can produce stitch-friendly routing solutions and thus greatly improve MEBL manufacturability and yield.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Stitch-Aware Routing Considering Smart Boundary for Multiple E-Beam Lithography\",\"authors\":\"Chih-Hsiang Hsu, Shao-Yun Fang\",\"doi\":\"10.1109/VLSI-DAT49148.2020.9196298\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As one of competitive next generation lithography (NGL), multiple electron beam lithography (MEBL) has been proposed to improve the low throughput issue. For this maskless lithography, each field is split into stripes that are slightly overlapped with each other, and each stripe of layout patterns is written by a single electron beam (e-beam). If a pattern lies on an overlapped region (stitching region) of two neighboring stripes, it can be written by either of the two e-beams, which is known as smart boundary. To avoid layout features written by more than one e-beam and thus suffering from the overlay error between different beams, we propose a full-chip router utilizing smart boundary to minimize stitch-sensitive patterns. Experimental results show that the proposed algorithm can produce stitch-friendly routing solutions and thus greatly improve MEBL manufacturability and yield.\",\"PeriodicalId\":235460,\"journal\":{\"name\":\"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"volume\":\"116 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-DAT49148.2020.9196298\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196298","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Stitch-Aware Routing Considering Smart Boundary for Multiple E-Beam Lithography
As one of competitive next generation lithography (NGL), multiple electron beam lithography (MEBL) has been proposed to improve the low throughput issue. For this maskless lithography, each field is split into stripes that are slightly overlapped with each other, and each stripe of layout patterns is written by a single electron beam (e-beam). If a pattern lies on an overlapped region (stitching region) of two neighboring stripes, it can be written by either of the two e-beams, which is known as smart boundary. To avoid layout features written by more than one e-beam and thus suffering from the overlay error between different beams, we propose a full-chip router utilizing smart boundary to minimize stitch-sensitive patterns. Experimental results show that the proposed algorithm can produce stitch-friendly routing solutions and thus greatly improve MEBL manufacturability and yield.