Automatic Floorplanning for AI SoCs

Abstract

In recent years, artificial intelligence/deep learning field is growing rapidly. The AI system-on-chip designs are actively developed. These designs often have properties of many IP blocks/embedded memories and complicated logic interconnect. In this paper, we propose an automatic floorplanning algorithm by using dataflow information and design exploration techniques to obtain high quality mixed macro and cell placement to handle numerous macros and complicated logic interconnect in AI SoCs.