用于60ghz无线互连的毫米波频率合成器

2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2020-08-01 DOI:10.1109/VLSI-DAT49148.2020.9196262

Yong-Yu Lin, Fan-ta Chen, Wei-Zen Chen

{"title":"用于60ghz无线互连的毫米波频率合成器","authors":"Yong-Yu Lin, Fan-ta Chen, Wei-Zen Chen","doi":"10.1109/VLSI-DAT49148.2020.9196262","DOIUrl":null,"url":null,"abstract":"A millimeter-wave (mmW) frequency synthesizer for 60GHz wireless transceiver is presented. To achieve wide range and low noise operation, a new sampling PD based PLL (S-PLL) is proposed. In contrast to conventional sub-sampling PD based PLLs, it provides a wider capture range without suffering from harmonic lock problems. Also, compared to conventional CP-based PLLs, the inband noise is improved by 13 dB while the reference spur is improved by more than 16 dB. Implemented in TSMC 28nm CMOS technology, the core circuit occupies a chip area of 0.175mm2. The measured phase noise from a 48 GHz carrier is -95.7dBc/Hz at 1MHz offset. The power consumption is 54mW.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A Millimeter-Wave Frequency Synthesizer for 60 GHz Wireless Interconnect\",\"authors\":\"Yong-Yu Lin, Fan-ta Chen, Wei-Zen Chen\",\"doi\":\"10.1109/VLSI-DAT49148.2020.9196262\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A millimeter-wave (mmW) frequency synthesizer for 60GHz wireless transceiver is presented. To achieve wide range and low noise operation, a new sampling PD based PLL (S-PLL) is proposed. In contrast to conventional sub-sampling PD based PLLs, it provides a wider capture range without suffering from harmonic lock problems. Also, compared to conventional CP-based PLLs, the inband noise is improved by 13 dB while the reference spur is improved by more than 16 dB. Implemented in TSMC 28nm CMOS technology, the core circuit occupies a chip area of 0.175mm2. The measured phase noise from a 48 GHz carrier is -95.7dBc/Hz at 1MHz offset. The power consumption is 54mW.\",\"PeriodicalId\":235460,\"journal\":{\"name\":\"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"volume\":\"98 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-DAT49148.2020.9196262\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196262","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

介绍了一种用于60GHz无线收发器的毫米波频率合成器。为了实现大范围低噪声工作，提出了一种基于采样PD的新型锁相环(S-PLL)。与传统的基于分采样PD的锁相环相比，它提供了更宽的捕获范围，而不会出现谐波锁问题。此外，与传统的基于cp的锁相环相比，带内噪声提高了13 dB，而参考杂散提高了16 dB以上。核心电路采用台积电28nm CMOS技术，芯片面积为0.175mm2。在1MHz偏移时，48 GHz载波的相位噪声测量值为-95.7dBc/Hz。功耗54mW。

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A Millimeter-Wave Frequency Synthesizer for 60 GHz Wireless Interconnect

A millimeter-wave (mmW) frequency synthesizer for 60GHz wireless transceiver is presented. To achieve wide range and low noise operation, a new sampling PD based PLL (S-PLL) is proposed. In contrast to conventional sub-sampling PD based PLLs, it provides a wider capture range without suffering from harmonic lock problems. Also, compared to conventional CP-based PLLs, the inband noise is improved by 13 dB while the reference spur is improved by more than 16 dB. Implemented in TSMC 28nm CMOS technology, the core circuit occupies a chip area of 0.175mm2. The measured phase noise from a 48 GHz carrier is -95.7dBc/Hz at 1MHz offset. The power consumption is 54mW.

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2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

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