{"title":"A Cost-Effective Embedded Nonvolatile Memory with Scalable LEE Flash®-G2 SONOS for Secure IoT and Computing-in-Memory (CiM) Applications","authors":"K. Nii, Y. Taniguchi, K. Okuyama","doi":"10.1109/VLSI-DAT49148.2020.9196270","DOIUrl":null,"url":null,"abstract":"We introduce a cost-effective, reliable and energy efficient embedded flash memory technology and its applications. A charge trapping type of Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) with twin select-gates structure has been demonstrated on 55-nm bulk CMOS technology. It is potentially scalable on advanced fully depleted (FD)-SOI or 3D Fin-FET devices below 28-nm node. Those feasibilities are shown by TCAD simulations and existing 55-nm planar bulk silicon data. Secure and low-power applications are introduced that are using nonvolatile (NV)-SRAM by combining with SRAM cell and flash cell. Besides, analog computing-inmemory (CiM) based on flash is also introduced for energy efficient artificial intelligence (AI) applications in edge computing.","PeriodicalId":235460,"journal":{"name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"310 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT49148.2020.9196270","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
We introduce a cost-effective, reliable and energy efficient embedded flash memory technology and its applications. A charge trapping type of Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) with twin select-gates structure has been demonstrated on 55-nm bulk CMOS technology. It is potentially scalable on advanced fully depleted (FD)-SOI or 3D Fin-FET devices below 28-nm node. Those feasibilities are shown by TCAD simulations and existing 55-nm planar bulk silicon data. Secure and low-power applications are introduced that are using nonvolatile (NV)-SRAM by combining with SRAM cell and flash cell. Besides, analog computing-inmemory (CiM) based on flash is also introduced for energy efficient artificial intelligence (AI) applications in edge computing.