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1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

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Ku-band FET oscillator ku波段FET振荡器
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156137
F. Sechi, J. Brown
{"title":"Ku-band FET oscillator","authors":"F. Sechi, J. Brown","doi":"10.1109/ISSCC.1980.1156137","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156137","url":null,"abstract":"An FET oscillator, tunable from 16.0-16.5GHz, offering up to 19% efficiency and an output power of 100mW, will be described.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133732932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Direct IC pattern generation by laser writing 用激光写入直接生成IC图案
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156073
J. Moulic, W. Kleinfelder
{"title":"Direct IC pattern generation by laser writing","authors":"J. Moulic, W. Kleinfelder","doi":"10.1109/ISSCC.1980.1156073","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156073","url":null,"abstract":"A flexible IC pattern-generating laser, tool enabling modification of features by direct photoresist exposure, while viewing existing patterns, will be covered. Technique eliminates need for precision registration alignment.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"2010 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114539815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The silicon telephone line interface circuits challenge 硅电话线路接口电路的挑战
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156103
H. Mussman, P. Gray
{"title":"The silicon telephone line interface circuits challenge","authors":"H. Mussman, P. Gray","doi":"10.1109/ISSCC.1980.1156103","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156103","url":null,"abstract":"Typically, a transformer is used to provide the battery feed and hybrid functions in a telephone line interface circuit. Recently, several new approaches using silicon technology have been reported. Panel will compare them and seek to predict which can be economically applied to global Central Office and PBX applications.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125138114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 42Mb partially asynchronous code converter for digital signal processing in telephony 用于电话数字信号处理的42Mb部分异步代码转换器
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156032
G. Baldwin, S. Tewksbury, V. Archer, N. Linde, Chi-Yu Kao
{"title":"A 42Mb partially asynchronous code converter for digital signal processing in telephony","authors":"G. Baldwin, S. Tewksbury, V. Archer, N. Linde, Chi-Yu Kao","doi":"10.1109/ISSCC.1980.1156032","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156032","url":null,"abstract":"A partially asynchronous encoder using a bipolar IC that converts, in either direction, between compressed μ-law or A-law and linear telephony codes, will be described. Serial data can be interfaced at rates up to 42Mb.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130552662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Computer aided design tools for VLSI VLSI计算机辅助设计工具
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156095
R. Smith, R. Joy
{"title":"Computer aided design tools for VLSI","authors":"R. Smith, R. Joy","doi":"10.1109/ISSCC.1980.1156095","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156095","url":null,"abstract":"The computer-aided design segment of the IC industry has had some success with tools to help with the LSI design problem. Particularly, circuit and logic simulation, layout graphics, and design rule checking have been very useful. Other areas, such as testing and modeling, continue to present challenges at the LSI level. As VLSI structures become a reality, new magnitudes of CAD tools will be needed. Can existing tools be scaled to solve the problem or will new approaches be required?","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123761408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
MOS buried load logic MOS埋地负载逻辑
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156123
Y. Sakai, T. Masuhara, O. Minato, N. Hashimoto
{"title":"MOS buried load logic","authors":"Y. Sakai, T. Masuhara, O. Minato, N. Hashimoto","doi":"10.1109/ISSCC.1980.1156123","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156123","url":null,"abstract":"A MOS buried logic technique using buried JFET loads with a gate delay of 0.34ns and a power delay product of 0.17pJ will be reported. Development has been applied to a 4-stage binary counter operating with a maximum toggle of 72.4MHz.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"35 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132270741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
GaAs FET amplifier for a satellite transponder 卫星转发器用砷化镓场效应晶体管放大器
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156055
B. Dornan, You-sun Wu, H. Wolkstein, Ho-Chung Huang, F. Drago
{"title":"GaAs FET amplifier for a satellite transponder","authors":"B. Dornan, You-sun Wu, H. Wolkstein, Ho-Chung Huang, F. Drago","doi":"10.1109/ISSCC.1980.1156055","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156055","url":null,"abstract":"A space qualifiable GaA5 FET amplifier with 300MHz instantaneous bandwidth, 54dB power gain, 38% efficiency and 10W output in the 3.7-4.2GHz band, will be described.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130769372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A digital signal processor for telecommunications applications 一种用于电信应用的数字信号处理器
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156117
J. Boddie, G. Daryanani, I. Eldumiati, R. Gadenz, J. Thompson, S. Walters, R. Pedersen
{"title":"A digital signal processor for telecommunications applications","authors":"J. Boddie, G. Daryanani, I. Eldumiati, R. Gadenz, J. Thompson, S. Walters, R. Pedersen","doi":"10.1109/ISSCC.1980.1156117","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156117","url":null,"abstract":"This paper will report on a programmable digital signal processor chip which can decode on instruction, fetch data, perform a 16 × 20b multiply, and add the resultant to a 40b accumulator in 80ns. Circuit permits all signal processing functions of a dual-tone multifrequency receiver or a low-speed modem to be realized on one chip.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116698031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Monolithic and hybrid microwave ICs 单片和混合微波集成电路
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156096
W. Wisseman, J. Gewartowski
{"title":"Monolithic and hybrid microwave ICs","authors":"W. Wisseman, J. Gewartowski","doi":"10.1109/ISSCC.1980.1156096","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156096","url":null,"abstract":"Microwave ICs, using both hybrid and monolithic approaches, are being realized with both silicon and gallium arsenide technologies. The panel will discuss the advantages and limitations of the alternatives from performance, frequency, reliability and cost points of view.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116925380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 35,000-transistor chip VLSI echo canceler 一个35000晶体管芯片VLSI回声消除器
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156035
Yen-Sun Chen, D. Duttweiler
{"title":"A 35,000-transistor chip VLSI echo canceler","authors":"Yen-Sun Chen, D. Duttweiler","doi":"10.1109/ISSCC.1980.1156035","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156035","url":null,"abstract":"A single-chip VLSI echo canceler fabricated in 5μ Si-gate enhancement NMOS technology will be discussed. The chip, containing 2704 bits of dynamic shift register and 3300 logic gates, measures 313 × 356 mils.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134097091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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