MOS埋地负载逻辑

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1980.1156123

Y. Sakai, T. Masuhara, O. Minato, N. Hashimoto

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引用次数: 2

摘要

本文将报导一种利用埋藏JFET负载的MOS埋地逻辑技术，其栅极延迟为0.34ns，功率延迟积为0.17pJ。开发已应用于4级二进制计数器，最大切换频率为72.4MHz。

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MOS buried load logic

A MOS buried logic technique using buried JFET loads with a gate delay of 0.34ns and a power delay product of 0.17pJ will be reported. Development has been applied to a 4-stage binary counter operating with a maximum toggle of 72.4MHz.

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来源期刊

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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