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1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

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The effect of sea level cosmic rays on electronic devices 海平面宇宙射线对电子设备的影响
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1981-06-01 DOI: 10.1109/ISSCC.1980.1156060
J. Ziegler, W. Lanford
{"title":"The effect of sea level cosmic rays on electronic devices","authors":"J. Ziegler, W. Lanford","doi":"10.1109/ISSCC.1980.1156060","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156060","url":null,"abstract":"The evaluation of the effects of cosmic rays on computer memories and its application to typical memory devices will be discussed. Conclusions indicate that cosmic ray nucleons and muons could have a significant effect on the next generation of computer memory circuitry. Error rates increase rapidly with altitude, offering the potential of accelerated testing to make electronic equipment less sensitive to the cosmic rays.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130553304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 171
A numeric data processor 数字数据处理机
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1980-02-13 DOI: 10.1109/ISSCC.1980.1156144
R. Nave, J. Palmer
{"title":"A numeric data processor","authors":"R. Nave, J. Palmer","doi":"10.1109/ISSCC.1980.1156144","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156144","url":null,"abstract":"A 4-state HMOS ROM, with nearly 700 bits of RAM for an internal stack and 29,000 bits of ROM for microcode and constants for a math processor, will be described. To integrate multiply, divide, square root and transcendental functions, a 68-bit internal data path has been included, with fast shifter and allied hardware to correct rounding.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124737472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Limits of VLSI VLSI的极限
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156106
R. Pashley, L. Terman
{"title":"Limits of VLSI","authors":"R. Pashley, L. Terman","doi":"10.1109/ISSCC.1980.1156106","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156106","url":null,"abstract":"The industry is continuing to shrink devices and increase integration levels. The panel will discuss the fundamental limits and practical barriers to the on-going development of VLSI, including reliability and yield effects of scaling, hot electron trapping, soft errors, current density limitations, leakage and circuit design tradeoffs. The focus will be on technology, device and circuit considerations.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127126158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Interpolative PCM CODECs with multiplexed digital filters 带多路数字滤波器的插值PCM编解码器
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/isscc.1980.1156029
H. Kuwahara, H. Kosugi, K. Imai, O. Yumoto, M. Ohnishi, E. Amada, T. Okabe, H. Shirasu
{"title":"Interpolative PCM CODECs with multiplexed digital filters","authors":"H. Kuwahara, H. Kosugi, K. Imai, O. Yumoto, M. Ohnishi, E. Amada, T. Okabe, H. Shirasu","doi":"10.1109/isscc.1980.1156029","DOIUrl":"https://doi.org/10.1109/isscc.1980.1156029","url":null,"abstract":"A single-chip CODEC - a 32kHz sampling 12b linear AD/DA - with pre-post - filters implemented in I2L without trimruing, will be described. The digital filter chip is shared between four CODECs: it has a 88dB dynamic range and operates at 2MHz with 16b word length.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127333182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A dense gate matrix layout style for MOS LSI MOS大规模集成电路的密集栅极矩阵布局
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156074
A. Lopez, Hung-Fai Law
{"title":"A dense gate matrix layout style for MOS LSI","authors":"A. Lopez, Hung-Fai Law","doi":"10.1109/ISSCC.1980.1156074","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156074","url":null,"abstract":"This paper will discuss a layout style - gate matrix - for CMOS VLSI in the polysilicon gate technology. Approach, simplifying and unifying layout procedure by using an orderly structure, a matrix, characterized by rows of polysilicon and columns of diffusion, has been tested in a 20,000- transistor layout.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125006221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A 16Kb static MTL/I2L memory chip 一个16Kb的静态MTL/I2L存储器芯片
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156078
S. Wiedmann, K. Heuber, W. Klein
{"title":"A 16Kb static MTL/I2L memory chip","authors":"S. Wiedmann, K. Heuber, W. Klein","doi":"10.1109/ISSCC.1980.1156078","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156078","url":null,"abstract":"An experimental static MTL memory chip with 45/100ns access cycle and 170mW select power, fabricated in standard 2μm-epi bipolar process, will be described. The chip - 17.4mm2- features a design concept adaptable to a MTL memory cell.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123434498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Foreword integrated systems on a chip 前言片上集成系统
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156084
J. Plummer
{"title":"Foreword integrated systems on a chip","authors":"J. Plummer","doi":"10.1109/ISSCC.1980.1156084","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156084","url":null,"abstract":"As technology advances, it is becoming increasingly difficult to differentiate integrated circuits from integrated systems. Furthermore, the traditional separation of analog and digital circuits is disappearing as technologies which are capable of realizing both types of circuits on the same chip are developed. These trends have been on the horizon for several years; they have arrived at ISSCC 80.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XXIII 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129923472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Ultra-wideband medium-power GaAs MESFET amplifiers 超宽带中功率GaAs MESFET放大器
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156027
Hua Tserng, H. Macksey
{"title":"Ultra-wideband medium-power GaAs MESFET amplifiers","authors":"Hua Tserng, H. Macksey","doi":"10.1109/ISSCC.1980.1156027","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156027","url":null,"abstract":"The design and performance of 5-18GHz single and multi-stage GaAs MESFET amplifiers with 1O0-300mW output will be discussed.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128260891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 5V 64K EPROM utilizing redundant circuitry 利用冗余电路的5V 64K EPROM
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156043
V. McKenny
{"title":"A 5V 64K EPROM utilizing redundant circuitry","authors":"V. McKenny","doi":"10.1109/ISSCC.1980.1156043","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156043","url":null,"abstract":"A static 300ns, 200mW 64K EPROM, using a small floating gate type cell, together with yield-optimizing redundant circuitry, for matrix, column decoders, sense amplifiers and input data buffers, will be reported.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124611976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A single-chip digital signal processor for voiceband applications 用于语音波段应用的单芯片数字信号处理器
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156033
Y. Kawakami, T. Nishitani, E. Sugimoto, E. Yamauchi, M. Suzuki
{"title":"A single-chip digital signal processor for voiceband applications","authors":"Y. Kawakami, T. Nishitani, E. Sugimoto, E. Yamauchi, M. Suzuki","doi":"10.1109/ISSCC.1980.1156033","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156033","url":null,"abstract":"A single-chip digital signal processor utilizing parallel multiplier and 3μ NMOS technology will be presented. Development can implement 41 second-order digital filter sections for 8kHz sampling of voiceband signals.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"23 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120905448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
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