MOS大规模集成电路的密集栅极矩阵布局

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1980.1156074

A. Lopez, Hung-Fai Law

{"title":"MOS大规模集成电路的密集栅极矩阵布局","authors":"A. Lopez, Hung-Fai Law","doi":"10.1109/ISSCC.1980.1156074","DOIUrl":null,"url":null,"abstract":"This paper will discuss a layout style - gate matrix - for CMOS VLSI in the polysilicon gate technology. Approach, simplifying and unifying layout procedure by using an orderly structure, a matrix, characterized by rows of polysilicon and columns of diffusion, has been tested in a 20,000- transistor layout.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"A dense gate matrix layout style for MOS LSI\",\"authors\":\"A. Lopez, Hung-Fai Law\",\"doi\":\"10.1109/ISSCC.1980.1156074\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper will discuss a layout style - gate matrix - for CMOS VLSI in the polysilicon gate technology. Approach, simplifying and unifying layout procedure by using an orderly structure, a matrix, characterized by rows of polysilicon and columns of diffusion, has been tested in a 20,000- transistor layout.\",\"PeriodicalId\":229101,\"journal\":{\"name\":\"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1980.1156074\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1980.1156074","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 17

摘要

本文将讨论多晶硅栅极技术中CMOS超大规模集成电路的一种布局样式——栅极矩阵。方法，简化和统一的布局程序，采用有序的结构，矩阵的特点，以多晶硅行和扩散列，已在一个20000晶体管布局测试。

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A dense gate matrix layout style for MOS LSI

This paper will discuss a layout style - gate matrix - for CMOS VLSI in the polysilicon gate technology. Approach, simplifying and unifying layout procedure by using an orderly structure, a matrix, characterized by rows of polysilicon and columns of diffusion, has been tested in a 20,000- transistor layout.

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来源期刊

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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