{"title":"A 5V-only 64K dynamic RAM","authors":"L. White, Ngai Hong, D. Redwine, G. Rao","doi":"10.1109/ISSCC.1980.1156075","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156075","url":null,"abstract":"A 64K×1 dynamic RAM with a single 5V power supply, access/cycle time of 120/250ns and a die size of 34,000 square mils, using 3μm design rules, will be covered. Interlocked clock circuits, dynamic sense amplifier with active loads, double input address decoding circuitry and grounded substrate operation minimize shortchannel effects and maximize margins.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126371809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A wideband two-quadrant analog multiplier","authors":"B. Gilbert, P. Holloway","doi":"10.1109/ISSCC.1980.1156069","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156069","url":null,"abstract":"A multiplier design technique affording ± 0.25% accuracy with 100MHz signal bandwidth will be discussed. Although the circuit operates in current mode, the virtual-ground inputs permit operation from low-level voltages. Laser trimming is used to eliminate nonlinearities due to VBEmismatch.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126584910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Sauer, W. Kosonocky, P. Levine, F. Shallcross, J. Carnes, R. Dawson, S. Chen
{"title":"A CCD comb filter IC for TV receivers","authors":"D. Sauer, W. Kosonocky, P. Levine, F. Shallcross, J. Carnes, R. Dawson, S. Chen","doi":"10.1109/ISSCC.1980.1156114","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156114","url":null,"abstract":"This paper will describe a CCD comb filter with a linear variable gain BCCD input structure, automatic CCD input and output biasing and 10.7MHz on-chip clock drivers.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126786287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Iawata, S. Hattori, K. Uchimura, H. Shimizu, K. Ogasawara
{"title":"PCM CODEC and filter system","authors":"A. Iawata, S. Hattori, K. Uchimura, H. Shimizu, K. Ogasawara","doi":"10.1109/ISSCC.1980.1156056","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156056","url":null,"abstract":"Si-gate CMOS ICs for a C-R CODEC and switched capacitor filters will be described. Power dissipation is 68mW.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"50 1-2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126938130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A monolithic digital line interface circuit","authors":"A. Boleda, T. Thomas","doi":"10.1109/ISSCC.1980.1156044","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156044","url":null,"abstract":"A CMOS IC for clock recovery, speed conversion, multiplexing of PCM and signaling, synchronization, COOEC and microprocessor interfacing, will be covered.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121785648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}