A 5V-only 64K dynamic RAM

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1980.1156075

L. White, Ngai Hong, D. Redwine, G. Rao

引用次数: 8

Abstract

A 64K×1 dynamic RAM with a single 5V power supply, access/cycle time of 120/250ns and a die size of 34,000 square mils, using 3μm design rules, will be covered. Interlocked clock circuits, dynamic sense amplifier with active loads, double input address decoding circuitry and grounded substrate operation minimize shortchannel effects and maximize margins.

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5v - 64K动态RAM

本文将介绍一款64K×1动态RAM，采用单5V电源，访问/周期时间为120/250ns，采用3μm设计规则，芯片尺寸为34,000平方密耳。联锁时钟电路，带有源负载的动态感测放大器，双输入地址解码电路和接地基板操作，最大限度地减少短通道效应和最大化利润。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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